Datasheet
© 2005 Fairchild Semiconductor Corporation DS500272 www.fairchildsemi.com
April 2000
Revised January 2005
NC7WZ86 TinyLogic
UHS Dual 2-Input Exclusive-OR Gate
NC7WZ86
TinyLogic
UHS Dual 2-Input Exclusive-OR Gate
General Description
The NC7WZ86 is a dual 2-Input Exclusive-OR Gate from
Fairchild’s Ultra High Speed Series of TinyLogic
. The
device is fabricated with advanced CMOS technology to
achieve ultra high speed with high output drive while main-
taining low static power dissipation over a very broad V
CC
operating range. The device is specified to operate over
the 1.65V to 5.5V V
CC
range. The inputs and output are
high impedance when V
CC
is 0V. Inputs tolerate voltages
up to 7V independent of V
CC
operating voltage.
Features
■ Space saving US8 surface mount package
■ MicroPak
Pb-Free leadless package
■ Ultra High Speed; t
PD
2.9 ns typ into 50 pF at 5V V
CC
■ High Output Drive; ± 24 mA at 3V V
CC
■ Broad V
CC
Operating Range; 1.65V to 5.5V
■ Matches the performance of LCX when operated at 3.3V
■ Power down high impedance inputs/output
■ Overvoltage tolerant inputs facilitate 5V to 3V translation
■ Patented noise/EMI reduction circuitry implemented
Ordering Code:
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
IEEE/IEC
Pin Descriptions
Function Table
H = HIGH Logic Level L = LOW Logic Level
Connection Diagrams
(Top View)
Pin One Orientation Diagram
AAA represents Product Code Top Mark - see ordering code
Note: Orientation of Top Mark determines Pin One location. Read the top
product code mark left to right, Pin One is the lower left pin (see diagram).
Pad Assignments for MicroPak
(Top Thru View)
TinyLogic is a registered trademark of Fairchild Semiconductor Corporation. MicroPak is a trademark of Fairchild Semiconductor Corporation.
Product
Package Description Supplied AsOrder Package Code
Number Number Top Mark
NC7WZ86K8X MAB08A WZ86 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide 3k Units on Tape and Reel
NC7WZ86L8X MAC08A N7 Pb-Free 8-Lead MicroPak, 1.6 mm Wide 5k Units on Tape and Reel
Pin Names Description
A
n
, B
n
Input
Y
n
Output
Y
= A⊕B
Inputs Output
ABY
LLL
LHH
HLH
HHL