Datasheet

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NC7S08 — TinyLogic

HS 2-Input AND Gate

NC7S08 Rev. 1.9.0

March 2008

NC7S08

TinyLogic

HS 2-Input AND Gate

Features

■

Space saving SOT23 or SC70 5-lead package

■

Ultra small MicroPak™ Pb-Free leadless package

■

High Speed; t

3.5ns typ

■

Low Quiescent Power; I

1µA

■

Balanced Output Drive; 2mA I

, –2mA I

■

Broad V

Operating Range; 2V–6V

■

Balanced Propagation Delays

■

Specified for 3V operation

General Description

The NC7S08 is a single 2-Input high performance

CMOS AND Gate. Advanced Silicon Gate CMOS fabri-

cation assures high speed and low power circuit opera-

tion over a broad V

range. ESD protection diodes

inherently guard both inputs and output with respect to

the V

and GND rails. Three stages of gain between

inputs and outputs assures high noise immunity and

reduced sensitivity to input edge rate.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order

Number

Package

Number

Product Code

Top Mark Package Description Supplied As

NC7S08M5X MA05B 7S08 5-Lead SOT23, JEDEC MO-178,

1.6mm

3k Units on Tape and Reel

NC7S08P5X MAA05A S08 5-Lead SC70, EIAJ SC-88a,

1.25mm Wide

3k Units on Tape and Reel

NC7S08L6X MAC06A PP 6-Lead MicroPak, 1.0mm Wide 5k Units on Tape and Reel

Summary of content (11 pages)

PAGE 1
NC7S08 TinyLogic® HS 2-Input AND Gate Features General Description ■ Space saving SOT23 or SC70 5-lead package The NC7S08 is a single 2-Input high performance CMOS AND Gate. Advanced Silicon Gate CMOS fabrication assures high speed and low power circuit operation over a broad VCC range. ESD protection diodes inherently guard both inputs and output with respect to the VCC and GND rails. Three stages of gain between inputs and outputs assures high noise immunity and reduced sensitivity to input edge rate.
PAGE 2
Logic Symbol Pin Assignments for SC70 and SOT23 IEEE/IEC Function Table Y = AB (Top View) Inputs A Pad Assignments for MicroPak Output B Y L L L L H L H L L H H H H = HIGH Logic Level L = LOW Logic Level (Top Thru View) Pin Description Pin Names Description A, B Inputs Y Output NC No Connect ©1995 Fairchild Semiconductor Corporation NC7S08 Rev. 1.9.0 www.fairchildsemi.
PAGE 3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC IIK Parameter Supply Voltage –0.5V to +7.0V DC Input Diode Current @ VIN ≤ –0.5V @ VIN ≥ VCC +0.
PAGE 4
TA = –40°C to +85°C TA = +25°C Symbol VIH VIL VOH VOL Parameter VCC (V) Min. Conditions Typ. Max. Min. Max. HIGH Level Input Voltage 2.0 1.50 1.50 3.0-6.0 0.7 x VCC 0.7 x VCC LOW Level Input Voltage 2.0 0.50 0.50 3.0-6.0 0.3 x VCC 0.3 x VCC HIGH Level Output Voltage LOW Level Output Voltage 2.0 3.0 IOH = –20µA, VIN = VIH 1.90 2.0 1.90 2.90 3.0 2.90 4.5 4.40 4.5 4.40 6.0 5.90 6.0 5.90 3.0 VIN = VIH, IOH = –1.3mA 2.68 2.85 2.63 4.5 VIN = VIH, IOH = –2mA 4.
PAGE 5
TA = –40°C to +85°C TA = +25°C Symbol Parameter tPLH, tPHL Propagation Delay tTLH, tTHL Output Transition Time Min. VCC (V) Conditions Typ. Max. Min. Max. 5.0 CL = 15pF 3.5 15 2.0 CL = 50pF 20 100 125 3.0 11 27 35 4.5 8 20 25 6.0 7 17 21 5.0 CL = 15pF 3.0 10 2.0 CL = 50pF 25 125 155 3.0 16 35 45 4.5 11 25 31 6.0 9 21 26 2 10 10 CIN Input Capacitance Open CPD Power Dissipation Capacitance 5.
PAGE 6
Tape Format for SC70 and SOT23 Package Designator Tape Section Number Cavities Cavity Status Cover Tape Status M5X, P5X Leader (Start End) 125 (typ.) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (typ.) Empty Sealed Tape Dimensions inches (millimeters) Package Tape Size Dim A Dim B Dim F Dim Ko Dim P1 Dim W SC70-5 8mm 0.093 (2.35) 0.096 (2.45) 0.138 ± 0.004 (3.5 ± 0.10) 0.053 ± 0.004 (1.35 ± 0.10) 0.157 (4) 0.315 ± 0.004 (8 ± 0.1) SOT23-5 8mm 0.130 (3.
PAGE 7
Tape Format for MicroPak Package Designator Tape Section Number Cavities Cavity Status Cover Tape Status L6X Leader (Start End) 125 (typ.) Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (typ.) Empty Sealed Reel Dimensions inches (millimeters) Tape Size A B 8mm 7.0 (177.8) 0.059 (1.50) ©1995 Fairchild Semiconductor Corporation NC7S08 Rev. 1.9.0 C D N 0.512 0.795 2.165 (13.00) (20.20) (55.00) W1 W2 W3 0.331 + 0.059/–0.000 (8.40 + 1.50/–0.00) 0.567 (14.40) W1 + 0.
PAGE 8
CL 3.00 2.80 5 0.95 A 0.95 4 B 3.00 2.60 1.70 1.50 1 2 2.60 3 (0.30) 1.00 0.50 0.30 0.95 1.90 0.20 C A B 0.70 TOP VIEW LAND PATTERN RECOMMENDATION SEE DETAIL A 1.30 0.90 1.45 MAX 0.15 0.05 0.22 0.08 C 0.10 C NOTES: UNLESS OTHEWISE SPECIFIED GAGE PLANE A) THIS PACKAGE CONFORMS TO JEDEC MO-178, ISSUE B, VARIATION AA, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) MA05Brev5 0.25 8° 0° 0.55 0.35 0.60 REF SEATING PLANE Figure 4. 5-Lead SOT23, JEDEC MO-178, 1.
PAGE 9
NC7S08 — TinyLogic® HS 2-Input AND Gate Physical Dimensions (Continued) Figure 5. 5-Lead SC70, EIAJ SC-88a, 1.25mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 10
2X 0.05 C 1.45 B 2X (1) 0.05 C (0.49) 5X 1.00 (0.75) (0.52) 1X A TOP VIEW 0.55MAX (0.30) 6X PIN 1 0.05 C 0.05 0.00 RECOMMENED LAND PATTERN 0.05 C C DETAIL A 0.25 0.15 6X 1.0 0.10 0.05 0.45 0.35 0.10 0.00 6X C B A C 0.40 0.30 0.35 5X 0.25 0.40 5X 0.30 (0.05) 6X 0.5 BOTTOM VIEW 0.075 X 45 CHAMFER DETAIL A PIN 1 TERMINAL (0.13) 4X Notes: 1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD 2. DIMENSIONS ARE IN MILLIMETERS 3. DRAWING CONFORMS TO ASME Y14.5M-1994 MAC06AREVC Figure 6.
PAGE 11
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