Datasheet

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MM74HCU04 — Hex Inverter

MM74HCU04 Rev. 1.4.0

February 2008

MM74HCU04

Hex Inverter

Features

■

Typical propagation delay: 7ns

■

Fanout of 15 LS-TTL loads

■

Quiescent power consumption: 10µA maximum at

room temperature

■

Low input current: 1µA maximum

General Description

The MM74HCU04 inverters utilize advanced silicon-gate

CMOS technology to achieve operating speeds similar to

LS-TTL gates with the low power consumption of stan-

dard CMOS integrated circuits.

The MM74HCU04 is an unbuffered inverter. It has high

noise immunity and the ability to drive 15 LS-TTL loads.

The 74HCU logic family is functionally as well as pin-out

compatible with the standard 74LS logic family. All inputs

are protected from damage due to static discharge by

internal diode clamps to V

and ground.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order Number

Package

Number Package Description

MM74HCU04M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

MM74HCU04SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HCU04MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

MM74HCU04N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Summary of content (10 pages)

PAGE 1
MM74HCU04 Hex Inverter Features General Description ■ Typical propagation delay: 7ns The MM74HCU04 inverters utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits. ■ Fanout of 15 LS-TTL loads ■ Quiescent power consumption: 10µA maximum at room temperature Low input current: 1µA maximum ■ The MM74HCU04 is an unbuffered inverter.
PAGE 2
MM74HCU04 — Hex Inverter Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Top View Schematic Diagram ©1983 Fairchild Semiconductor Corporation MM74HCU04 Rev. 1.4.0 www.fairchildsemi.
PAGE 3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Rating VCC Supply Voltage VIN DC Input Voltage –1.5 to VCC+1.5V DC Output Voltage –0.5 to VCC+0.
PAGE 4
TA = –40°C to 85°C TA = 25°C Symbol VIH VIL VOH VOL Parameter VCC (V) Conditions Typ. TA = –55°C to 125°C Guaranteed Limits Minimum HIGH Level Input Voltage 2.0 1.7 1.7 1.7 4.5 3.6 3.6 3.6 6.0 4.8 4.8 4.8 Maximum LOW Level Input Voltage 2.0 0.3 0.3 0.3 4.5 0.8 0.8 0.8 6.0 1.1 1.1 1.1 2.0 1.8 1.8 1.8 4.5 4.0 4.0 4.0 6.0 5.5 5.5 5.5 Minimum HIGH Level Output Voltage Maximum LOW Level Output Voltage 2.0 4.5 VIN = VIL, |IOUT| ≤ 20µA 6.0 4.
PAGE 5
TA=25°C Symbol tPHL, tPLH tTLH, tTHL Parameter Conditions VCC (V) Typ. Maximum Propagation Delay Maximum Output Rise and Fall Time CPD Power Dissipation Capacitance(4) CIN Maximum Input Capacitance (per gate) TA = –40°C to 85°C TA –55°C to 125°C Guaranteed Limits Units 2.0 49 82 103 120 4.5 9.9 16 21 24 6.0 8.4 14 18 20 2.0 30 75 95 110 4.5 8 15 19 22 6.0 7 13 16 19 90 8 ns ns pF 15 15 15 pF Note: 4.
PAGE 6
8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 (0.33) 1.75 MAX 1.50 1.25 1.27 LAND PATTERN RECOMMENDATION M C B A SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.
PAGE 7
MM74HCU04 — Hex Inverter Physical Dimensions (Continued) Figure 5. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
MM74HCU04 — Hex Inverter Physical Dimensions (Continued) 0.65 0.43 TYP 1.65 6.10 0.45 12.00° TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 6.
PAGE 9
MM74HCU04 — Hex Inverter Physical Dimensions (Continued) 19.56 18.80 14 8 6.60 6.09 1 7 (1.74) 8.12 7.62 1.77 1.14 3.56 3.30 0.35 0.20 5.33 MAX 0.38 MIN 3.81 3.17 0.58 0.35 8.82 2.54 NOTES: UNLESS OTHERWISE SPECIFIED THIS PACKAGE CONFORMS TO A) JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS ARE EXCLUSIVE OF BURRS, C) MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5-1994 E) DRAWING FILE NAME: MKT-N14AREV7 Figure 7.
PAGE 10
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