Datasheet

©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HCT74 Rev. 1.4.0 5
MM74HCT74 — Dual D-Type Flip-Flop with Preset and Clear
AC Electrical Characteristics
V
CC
= 5.0V ± 10%, C
L
= 50 pF, t
r
= t
f
= 6ns unless otherwise specified.
Note:
5. C
PD
determines the no load dynamic power consumption, P
D
= C
PD
V
CC
2
f + I
CC
V
CC
, and the no load dynamic
current consumption, I
S
= C
PD
V
CC
f + I
CC
.
Symbol Parameter Conditions
T
A
= 25°C T
A
= –40° to +85°C
UnitsTyp. Guaranteed Limits
f
MAX
Maximum Operating Frequency 27 21 MHz
t
PHL
, t
PLH
Maximum Propagation Delay from
Clock to Q or Q
21 35 44 ns
t
PHL
, t
PLH
Maximum Propagation Delay from
Preset or Clear to Q or Q
21 35 44 ns
t
REM
Minimum Removal Time Preset or
Clear to Clock
20 25 ns
t
S
Minimum Setup Time Data to
Clock
20 25 ns
t
H
Minimum Hold Time Clock to Data –3 0 0 ns
t
W
Minimum Pulse Width Clock,
Preset or Clear
916 20 ns
t
r
, t
f
Maximum Clock Input Rise and
Fall Time
500 500 ns
t
THL
, t
TLH
Maximum Output Rise and Fall
Time
15 19 ns
C
PD
Power Dissipation Capacitance
(5)
(per flip-flop) 10 pF
C
IN
Maximum Input Capacitance 5 10 10 pF