Datasheet

©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HCT74 Rev. 1.4.0 2
MM74HCT74 — Dual D-Type Flip-Flop with Preset and Clear
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Truth Table
Q0 = the level of Q before the indicated input conditions
were established.
Note:
1. This configuration is nonstable; that is, it will not persist
when preset and clear inputs return to their inactive
(HIGH) level.
Logic Diagram
Inputs Outputs
PR CLR CLK D Q Q
LHXXHL
HLXXLH
LLXXH
(1)
H
(1)
HH ↑ HHL
HH ↑ LLH
HHLXQ0 Q
0