Datasheet

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February 1984

Revised May 2005

MM74HCT273 Octal D-Type Flip-Flop with Clear

MM74HCT273

Octal D-Type Flip-Flop with Clear

General Description

The MM74HCT273 utilizes advanced silicon-gate CMOS

technology. It has an input threshold and output drive simi-

lar to LS-TTL with the low standby power of CMOS.

These positive edge-triggered flip-flops have a common

clock and clear-independent Q outputs. Data on a D input,

having the specified set-up and hold time, is transferred to

the corresponding Q output on the positive-going transition

of the clock pulse. The asynchronous clear forces all out-

puts LOW when it is LOW.

All inputs to this device are protected from damage due to

electrostatic discharge by diodes to V

and ground.

MM74HCT devices are intended to interface TTL and

NMOS components to CMOS components. These parts

can be used as plug-in replacements to reduce system

power consumption in existing designs.

Features

■ Typical propagation delay: 20 ns

■ Low quiescent current: 80 A maximum (74HCT series)

■ Fanout of 10 LS-TTL loads

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Assignments for DIP, SOIC, SOP and TSSOP

Top View

Order Number

Package

Number

Package Description

MM74HCT273WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

MM74HCT273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HCT273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HCT273N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Summary of content (8 pages)

PAGE 1
Revised May 2005 MM74HCT273 Octal D-Type Flip-Flop with Clear General Description Features The MM74HCT273 utilizes advanced silicon-gate CMOS technology. It has an input threshold and output drive similar to LS-TTL with the low standby power of CMOS. ■ Typical propagation delay: 20 ns ■ Low quiescent current: 80 PA maximum (74HCT series) ■ Fanout of 10 LS-TTL loads These positive edge-triggered flip-flops have a common clock and clear-independent Q outputs.
PAGE 2
MM74HCT273 Truth Table (Each Flip-Flop) Inputs Outputs Clear Clock D L X X L H n H H H n L L H L X Q0 H HIGH Level (steady-state) L LOW Level (steady-state) X Don’t Care n Transition from LOW-to-HIGH level Q0 The level of Q before the indicated steady-state input conditions were established. Logic Diagram www.fairchildsemi.
PAGE 3
Recommended Operating Conditions Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per Pin (IOUT) DC VCC or GND Current, per Pin (ICC) Storage Temperature Range (TSTG) 0.5V to 7.0V 1.5V to VCC 1.5V 0.5V to VCC 0.5V r20 mA r25 mA r50 mA 65qC to 150qC Supply Voltage (VCC) 600 mW S.O. Package only 500 mW Max Units 4.5 5.
PAGE 4
MM74HCT273 AC Electrical Characteristics VCC 5V, TA 25qC, CL 15 pF, tr Symbol tf 6 ns Parameter Conditions Typ Guaranteed Limits Units fMAX Maximum Operating Frequency 68 30 tPHL, tPLH Maximum Propagation Delay from Clock to Q 18 30 MHz ns tPHL, tPLH Maximum Propagation Delay from Clear to Q 21 30 ns ns tREM Minimum Removal Time, Clear to Clock 1 5 tS Minimum Set-Up Time D to Clock 6 20 ns tH Minimum Hold Time Clock to D 3 5 ns tW Minimum Pulse Width Clock or Clear
PAGE 5
MM74HCT273 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.
PAGE 6
MM74HCT273 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.
PAGE 7
MM74HCT273 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.
PAGE 8
MM74HCT273 Octal D-Type Flip-Flop with Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.