Datasheet

February 1984
Revised February 1999
MM74HCT138 3-to-8 Line Decoder
© 1999 Fairchild Semiconductor Corporation DS005362.prf www.fairchildsemi.com
MM74HCT138
3-to-8 Line Decoder
General Description
The MM74HCT138 decoder utilizes advanced silicon-gate
CMOS technology, and are well suited to memory address
decoding or data routing applications. Both circuits feature
high noise immunity and low power consumption usually
associated with CMOS circuitry, yet have speeds compara-
ble to low power Schottky TTL logic.
The MM74HCT138 have 3 binary select inputs (A, B, and
C). If the device is enabled these inputs determine which
one of the eight normally HIGH outputs will go LOW. Two
active LOW and one active HIGH enables (G1, G2A and
G2B) are provided to ease the cascading decoders.
The decoders’ output can drive 10 low power Schottky TTL
equivalent loads and are functionally and pin equivalent to
the 74LS138. All inputs are protected from damage due to
static discharge by diodes to V
CC
and ground.
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug-in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
Features
■ TTL input compatible
■ Typical propagation delay: 20 ns
■ Low quiescent current: 80 µA maximum (74HCT Series)
■ Low input current: 1 µA maximum
■ Fanout of 10 LS-TTL loads
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Order Number Package Number Package Description
MM74HCT138M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HCT138SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT138MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT138N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide