Datasheet

©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HC74A Rev. 1.3.0 6
MM74HC74A — Dual D-Type Flip-Flop with Preset and Clear
AC Electrical Characteristics
C
L
= 50 pF, t
r
= t
f
= 6ns (unless otherwise specified)
Note:
5. C
PD
determines the no load dynamic power consumption, P
D
= C
PD
V
CC
2
f + I
CC
V
CC
, and the no load dynamic
current consumption, I
S
= C
PD
V
CC
f + I
CC
.
Symbol Parameter Conditions V
CC
(V)
T
A
= 25°C
T
A
= –40°C
to 85°C
T
A
= –55°C
to 125°C
UnitsTyp. Guaranteed Limits
f
MAX
Maximum Operating
Frequency
2.0 22 6 5 4 MHz
4.5 72 30 24 20
6.0 94 35 28 24
t
PHL
, t
PLH
Maximum Propagation
Delay Clock to Q or Q
2.0 34 110 140 165 ns
4.5 12 22 28 33
6.0 10 19 24 28
t
PHL
, t
PLH
Maximum Propagation
Delay Preset or Clear
to Q or Q
2.0 66 150 190 225 ns
4.5 20 30 38 45
6.0 16 26 33 38
t
REM
Minimum Removal
Time, Preset or Clear
to Clock
2.0 20 50 65 75 ns
4.5 6 10 13 15
6.0 5 9 11 13
t
s
Minimum Setup Time
Data to Clock
2.0 35 80 100 120 ns
4.5 10 16 20 24
6.0 8 14 17 20
t
H
Minimum Hold Time
Clock to Data
2.0 0 0 0 ns
4.5 0 0 0
6.0 0 0 0
t
W
Minimum, Pulse Width
Clock, Preset or Clear
2.0 30 80 101 119 ns
4.5 9 16 20 24
6.0 8 14 17 20
t
TLH
, t
THL
Maximum Output
Rise and Fall Time
2.0 25 75 95 110 ns
4.5V 7 15 19 22
6.0V 6 13 16 19
t
r
, t
f
Maximum Input Rise
and Fall Time
2.0 1000 1000 1000 ns
4.5 500 500 500
6.0 400 400 400
C
PD
Power Dissipation
Capacitance
(5)
(per flip-flop) 80 pF
C
IN
Maximum Input
Capacitance
510 10 10 pF