Datasheet

©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HC74A Rev. 1.3.0 2
MM74HC74A — Dual D-Type Flip-Flop with Preset and Clear
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Truth Table
Note:
Q0 = the level of Q before the indicated input conditions
were established.
1. This configuration is nonstable; that is, it will not persist
when preset and clear inputs return to their inactive
(HIGH) level.
Logic Diagram
Inputs Outputs
PR CLR CLK D Q Q
LH XX H L
HL XX L H
LL XX H
(1)
H
(1)
HH ↑ HH L
HH ↑ LL H
HH LX Q0 Q
0