Datasheet

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September 1983

Revised May 2005

MM74HC373 3-STATE Octal D-Type Latch

MM74HC373

3-STATE Octal D-Type Latch

General Description

The MM74HC373 high speed octal D-type latches utilize

advanced silicon-gate CMOS technology. They possess

the high noise immunity and low power consumption of

standard CMOS integrated circuits, as well as the ability to

drive 15 LS-TTL loads. Due to the large output drive capa-

bility and the 3-STATE feature, these devices are ideally

suited for interfacing with bus lines in a bus organized sys-

tem.

When the LATCH ENABLE input is HIGH, the Q outputs

will follow the D inputs. When the LATCH ENABLE goes

LOW, data at the D inputs will be retained at the outputs

until LATCH ENABLE returns HIGH again. When a high

logic level is applied to the OUTPUT CONTROL input, all

outputs go to a high impedance state, regardless of what

signals are present at the other inputs and the state of the

storage elements.

The 74HC logic family is speed, function, and pin-out com-

patible with the standard 74LS logic family. All inputs are

protected from damage due to static discharge by internal

diode clamps to V

and ground.

Features

■ Typical propagation delay: 18 ns

■ Wide operating voltage range: 2 to 6 volts

■ Low input current: 1 A maximum

■ Low quiescent current: 80 A maximum (74 Series)

■ Output drive capability: 15 LS-TTL loads

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Assignments for DIP, SOIC, SOP and TSSOP

Top View

Truth Table

H HIGH Level

LOW Level

Level of output before steady-state input conditions were established.

High Impedance

Order Number Package Number Package Description

MM74HC373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

MM74HC373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HC373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Output Latch Data 373

Control Enable Output

LHHH

LHLL

LLXQ

HXXZ

Summary of content (8 pages)

PAGE 1
Revised May 2005 MM74HC373 3-STATE Octal D-Type Latch General Description Features The MM74HC373 high speed octal D-type latches utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. Due to the large output drive capability and the 3-STATE feature, these devices are ideally suited for interfacing with bus lines in a bus organized system.
PAGE 2
MM74HC373 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) Supply Voltage (VCC) DC Input Voltage (VIN ) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) 0.5 to 7.0V 1.5 to VCC 1.5V 0.5 to VCC 0.5V r20 mA r35 mA r70 mA 65qC to 150qC Supply Voltage (VCC) 600 mW S.O.
PAGE 3
MM74HC373 AC Electrical Characteristics VCC 5V, TA 25qC, tr tf 6 ns Symbol Parameter Conditions Guaranteed Typ Limit Units tPHL, tPLH Maximum Propagation Delay, Data to Q CL 45 pF 18 25 ns tPHL, tPLH Maximum Propagation Delay, LE to Q CL 45 pF 21 30 ns tPZH, tPZL Maximum Output Enable Time RL 1 k: 20 28 ns CL 45 pF RL 1 k: 18 25 ns CL 5 pF tPHZ, tPLZ Maximum Output Disable Time tS Minimum Set Up Time 5 ns tH Minimum Hold Time 10 ns tW Minimum Pulse Width
PAGE 4
MM74HC373 AC Electrical Characteristics Symbol COUT Parameter (Continued) Conditions VCC Maximum Output TA 25qC Typ 15 TA 40 to 85qC TA 55 to 125qC 20 20 20 Capacitance Note 5: CPD determines the no load dynamic power consumption, PD IS CPD VCC f ICC. www.fairchildsemi.
PAGE 5
MM74HC373 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.
PAGE 6
MM74HC373 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.
PAGE 7
MM74HC373 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.
PAGE 8
MM74HC373 3-STATE Octal D-Type Latch Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.