Datasheet

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September 1983

Revised May 2005

MM74HC273 Octal D-Type Flip-Flops with Clear

MM74HC273

Octal D-Type Flip-Flops with Clear

General Description

The MM74HC273 edge triggered flip-flops utilize advanced

silicon-gate CMOS technology to implement D-type flip-

flops. They possess high noise immunity, low power, and

speeds comparable to low power Schottky TTL circuits.

This device contains 8 master-slave flip-flops with a com-

mon clock and common clear. Data on the D input having

the specified setup and hold times is transferred to the Q

output on the LOW-to-HIGH transition of the CLOCK input.

The CLEAR input when LOW, sets all outputs to a low

state.

Each output can drive 10 low power Schottky TTL equiva-

lent loads. The MM74HC273 is functionally as well as pin

compatible to the 74LS273. All inputs are protected from

damage due to static discharge by diodes to V

and

ground.

Features

■ Typical propagation delay: 18 ns

■ Wide operating voltage range

■ Low input current: 1 A maximum

■ Low quiescent current: 80 A (74 Series)

■ Output drive: 10 LS-TTL loads

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Top View

Order Number Package Number Package Description

MM74HC273WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

MM74HC273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HC273N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Summary of content (8 pages)

PAGE 1
Revised May 2005 MM74HC273 Octal D-Type Flip-Flops with Clear General Description Features The MM74HC273 edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flipflops. They possess high noise immunity, low power, and speeds comparable to low power Schottky TTL circuits. This device contains 8 master-slave flip-flops with a common clock and common clear.
PAGE 2
MM74HC273 Truth Table Logic Diagram (Each Flip-Flop) Inputs Outputs Clear Clock D L X X Q L H H H H n n L L H L X Q0 H HIGH Level (Steady State) L LOW Level (Steady State) X Don’t Care n Transition from LOW-to-HIGH level Q0 The level of Q before the indicated steady state input conditions were established www.fairchildsemi.
PAGE 3
Recommended Operating Conditions Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) 0.5 to 7.0V 1.5 to VCC 1.5V 0.5 to VCC 0.5V r20 mA r25 mA r50 mA 65qC to 150qC Supply Voltage (VCC) 600 mW S.O.
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MM74HC273 AC Electrical Characteristics VCC 5V, TA 25qC, CL 15 pF, tr Symbol tf 6 ns Parameter Conditions Guaranteed Typ Limit Units fMAX Maximum Operating Frequency 50 30 MHz tPHL, tPLH Maximum Propagation 18 27 ns 18 27 ns 10 20 ns 10 20 ns 2 0 ns 10 16 ns Delay, Clock to Output tPHL Maximum Propagation Delay, Clear to Output Minimum Removal Time, tREM Clear to Clock ts Minimum Setup Time Data to Clock tH Minimum Hold Time Clock to Data Minimum Pulse Width tW
PAGE 5
MM74HC273 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.
PAGE 6
MM74HC273 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.
PAGE 7
MM74HC273 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.
PAGE 8
MM74HC273 Octal D-Type Flip-Flops with Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.