Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsLogic ICsLogic IC - Buffer, driver TSSOP 20

September 1983

Revised May 2005

MM74HC240 Inverting Octal 3-STATE Buffer

MM74HC240

Inverting Octal 3-STATE Buffer

General Description

The MM74HC240 3-STATE buffer utilizes advanced sili-

con-gate CMOS technology. It possesses high drive cur-

rent outputs which enable high speed operation even when

driving large bus capacitances. These circuits achieve

speeds comparable to low power Schottky devices, while

retaining the advantage of CMOS circuitry, i.e., high noise

immunity and low power consumption. It has a fanout of 15

LS-TTL equivalent inputs.

The MM74HC240 is an inverting buffer and has two active

LOW enables (1G

and 2G). Each enable independently

controls 4 buffers.

All inputs are protected from damage due to static dis-

charge by diodes to V

and ground.

Features

■ Typical propagation delay: 12 ns

■ 3-STATE outputs for connection to system buses

■ Wide power supply range: 2–6V

■ Low quiescent supply current: 80 A (74 Series)

■ Output current: 6 mA

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Top View

Truth Table

H HIGH Level

LOW Level

HIGH Impedance

Order Number Package Number Package Description

MM74HC240WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

MM74HC240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC240MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HC240N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

1G 1A 1Y 2G 2A 2Y

LLHLLH

LHLLHL

HLZHLZ

HHZHHZ

Summary of content (8 pages)

PAGE 1
Revised May 2005 MM74HC240 Inverting Octal 3-STATE Buffer General Description Features The MM74HC240 3-STATE buffer utilizes advanced silicon-gate CMOS technology. It possesses high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits achieve speeds comparable to low power Schottky devices, while retaining the advantage of CMOS circuitry, i.e., high noise immunity and low power consumption. It has a fanout of 15 LS-TTL equivalent inputs.
PAGE 2
MM74HC240 Logic Diagram www.fairchildsemi.
PAGE 3
Recommended Operating Conditions 0.5 to 7.0V 1.5 to VCC 1.5V DC Output Voltage (VOUT) 0.5 to VCC 0.
PAGE 4
MM74HC240 AC Electrical Characteristics VCC 5V, TA 25qC, tr Symbol tf 6 ns Conditions Typ Guaranteed Limit Units tPHL, tPLH Maximum Propagation Delay CL 45 pF 12 18 ns tPZH, tPZL Maximum Enable Delay RL 1 k: to Active Output CL 45 pF 14 28 ns Maximum Disable Delay RL 1 k: from Active Output CL 5 pF 13 25 ns tPHZ, tPLZ Parameter AC Electrical Characteristics VCC 2.0V to 6.
PAGE 5
MM74HC240 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.
PAGE 6
MM74HC240 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.
PAGE 7
MM74HC240 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.
PAGE 8
MM74HC240 Inverting Octal 3-STATE Buffer Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.