Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsLogic ICsLogic IC - Flip-Flop Master rest Differential TSSOP 16

September 1983

Revised February 1999

MM74HC175 Quad D-Type Flip-Flop With Clear

MM74HC175

Quad D-Type Flip-Flop With Clear

General Description

The MM74HC175 high speed D-type flip-flop with comple-

mentary outputs utilizes advanced silicon-gate CMOS

technology to achieve the high noise immunity and low

power consumption of standard CMOS integrated circuits,

along with the ability to drive 10 LS-TTL loads.

Information at the D inputs of the MM74HC175 is trans-

ferred to the Q and Q

outputs on the positive going edge of

the clock pulse. Both true and complement outputs from

each flip flop are externally available. All four flip-flops are

controlled by a common clock and a common CLEAR.

Clearing is accomplished by a negative pulse at the

CLEAR input. All four Q outputs are cleared to a logical “0”

and all four Q

outputs to a logical “1.”

The 74HC logic family is functionally as well as pin-out

compatible with the standard 74LS logic family. All inputs

are protected from damage due to static discharge by inter-

nal diode clamps to V

and ground.

Features

■ Typical propagation delay: 15 ns

■ Wide operating supply voltage range: 2–6V

■ Low input current: 1 µA maximum

■ Low quiescent supply current: 80 µA maximum (74HC)

■ High output drive current: 4 mA minimum (74HC)

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Assignments for DIP, SOIC, SOP and TSSOP

Top View

Truth Table

(Each Flip-Flop)

H = HIGH Level (steady state)

L = LOW Level (steady state)

X = Irrelevant

↑ = Transition from LOW-to-HIGH level

= The level of Q before the indicated steady-state input conditions were

established

Order Number Package Number Package Description

MM74HC175M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

MM74HC175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HC175N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Inputs Outputs

Clear Clock D Q Q

LXXLH

H ↑ HH L

H ↑ LL H

HLXQ

Summary of content (7 pages)

PAGE 1
Revised February 1999 MM74HC175 Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity and low power consumption of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads. Information at the D inputs of the MM74HC175 is transferred to the Q and Q outputs on the positive going edge of the clock pulse.
PAGE 2
MM74HC175 Logic Diagram www.fairchildsemi.
PAGE 3
Recommended Operating Conditions −0.5 to +7.0V Supply Voltage (VCC) DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT) −0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK) ±20 mA DC Output Current, per pin (IOUT) ±25 mA Max Units 2 6 V 0 VCC V −40 +85 °C (tr, tf) VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 6.
PAGE 4
MM74HC175 AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol fMAX Parameter Conditions Guaranteed Typ Maximum Operating Limit Units 60 35 MHz 15 25 ns 13 21 ns 20 ns Frequency tPHL, tPLH Maximum Propagation Delay, Clock to Q or Q tPHL, tPLH Maximum Propagation Delay, Reset to Q or Q tREC Minimum Removal Time, Clear to Clock tS Minimum Setup Time, Data to Clock 20 ns tH Minimum Hold Time, Data from Clock 0 ns tW Minimum Pulse Width, Clock o
PAGE 5
MM74HC175 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 5 www.fairchildsemi.
PAGE 6
MM74HC175 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.
PAGE 7
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1.