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MM74HC125, MM74HC126 — 3-STATE Quad Buffers

MM74HC125, MM74HC126 Rev. 1.3.0

February 2008

MM74HC125, MM74HC126

3-STATE Quad Buffers

Features

■

Typical propagation delay: 13ns

■

Wide operating voltage range: 2V–6V

■

Low input current: 1µA maximum

■

Low quiescent current: 80µA maximum (74HC)

■

Fanout of 15 LS-TTL loads

General Description

The MM74HC125 and MM74HC126 are general pur-

pose 3-STATE high speed non-inverting buffers utilizing

advanced silicon-gate CMOS technology. They have

high drive current outputs which enable high speed oper-

ation even when driving large bus capacitances. These

circuits possess the low power dissipation of CMOS

circuitry, yet have speeds comparable to low power

Schottky TTL circuits. Both circuits are capable of driving

up to 15 low power Schottky inputs.

The MM74HC125 require the 3-STATE control input C to

be taken high to put the output into the high impedance

condition, whereas the MM74HC126 require the control

input to be low to put the output into high impedance.

All inputs are protected from damage due to static

discharge by diodes to V

and ground.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order Number

Package

Number Package Description

MM74HC125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"

Narrow

MM74HC125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

MM74HC125N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

MM74HC126M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"

Narrow

MM74HC126SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC126MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

MM74HC126N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Summary of content (10 pages)

PAGE 1
MM74HC125, MM74HC126 3-STATE Quad Buffers Features General Description ■ Typical propagation delay: 13ns The MM74HC125 and MM74HC126 are general purpose 3-STATE high speed non-inverting buffers utilizing advanced silicon-gate CMOS technology. They have high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits.
PAGE 2
Pin Assignments for DIP, SOIC, SOP and TSSOP Top View (MM74HC125) Top View (MM74HC126) Truth Tables Inputs Output Inputs Output A C Y A C Y H L H H H H L L L L H L X H Z X L Z MM74HC125 ©1983 Fairchild Semiconductor Corporation MM74HC125, MM74HC126 Rev. 1.3.0 MM74HC126 www.fairchildsemi.
PAGE 3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Rating VCC Supply Voltage VIN DC Input Voltage –1.5 to VCC+1.5V DC Output Voltage –0.5 to VCC+0.
PAGE 4
TA = 25°C Symbol VIH VIL VOH VOL Parameter Conditions VCC (V) Typ. TA = –40°C TA = –40°C to 85°C to 125°C Guaranteed Limits Minimum HIGH Level Input Voltage 2.0 1.5 1.5 1.5 4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 Maximum LOW Level Input Voltage 2.0 0.5 0.5 0.5 4.5 1.35 1.35 1.35 6.0 1.8 1.8 1.8 Minimum HIGH Level Output Voltage Maximum LOW Level Output Voltage VIN = VIH or VIL, |IOUT| ≤ 20µA 2.0 2.0 1.9 1.9 1.9 4.5 4.5 4.4 4.4 4.4 6.0 6.0 5.9 5.9 5.
PAGE 5
Symbol tPHL, tPLH Parameter Conditions Maximum Propagation Delay Time Typ. Guaranteed Limit Units 13 18 ns tPZH Maximum Output Enable Time to HIGH Level RL = 1kΩ 13 25 ns tPHZ Maximum Output Disable Time from HIGH Level RL = 1kΩ, CL = 5pF 17 25 ns tPZL Maximum Output Enable Time to LOW Level RL = 1kΩ 18 25 ns tPLZ Maximum Output Disable Time from LOW Level RL = 1kΩ, CL = 5pF 13 25 ns AC Electrical Characteristics VCC = 2.0V to 6.
PAGE 6
8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 (0.33) 1.75 MAX 1.50 1.25 1.27 LAND PATTERN RECOMMENDATION M C B A SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.
PAGE 7
MM74HC125, MM74HC126 — 3-STATE Quad Buffers Physical Dimensions (Continued) Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
MM74HC125, MM74HC126 — 3-STATE Quad Buffers Physical Dimensions (Continued) 0.65 0.43 TYP 1.65 6.10 0.45 12.00° TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 3.
PAGE 9
19.56 18.80 14 8 6.60 6.09 1 7 (1.74) 8.12 7.62 1.77 1.14 3.56 3.30 0.35 0.20 5.33 MAX 0.38 MIN 3.81 3.17 0.58 0.35 8.82 2.54 NOTES: UNLESS OTHERWISE SPECIFIED THIS PACKAGE CONFORMS TO A) JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS ARE EXCLUSIVE OF BURRS, C) MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5-1994 E) DRAWING FILE NAME: MKT-N14AREV7 Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.
PAGE 10
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