Datasheet

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FUSB2805 • Rev. 1.0.3 40
FUSB2805 — USB2.0 High-Speed OTG Transceiver with ULPI Interface
The FUSB2805 must follow the rules defined in Table
24 for setting any of the Latch register bits. If register
read data is returned to the link in the same cycle, a
USB interrupt latch bit is set, the interrupt condition is
given immediately in the register read data and the
latch bit is not set to 1b.
Table 24. Interrupt Latch Register Setting Rules
Input Conditions
Register Read Data Returned in
Current Clock Cycle
Interrupt Latch Bit Set (1b) in Current
Clock Cycle
Resultant Value of Latch
Register Bit
NO
NO
0b
NO
YES
1b
YES
NO
0b
YES
YES
0b
Debug Register (15h Read Only)
These register bits indicate the current values of various signals useful for debugging.
Table 25. Debug Register
Field Name
Bits
Access
Reset
Description
LineState0
0
rd
0b
Contains the current value of Linestate0
LineState1
1
rd
0b
Contains the current value of Linestate1
RESERVED
7:2
rd
0b
Reserved
Scratch Register (16h-18h Read, 16h Write, 17h Set, 18h Clear)
These register bits indicate the current values of various signals useful for debugging.
Table 26. Scratch Register
Field Name
Bits
Access
Reset
Description
Scratch
7:0
rd/wr/s/c
00h
Empty register byte for testing purposes. Software can read, write, set,
and clear this register and the FUSB2805 functionality is not affected.