Datasheet

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FUSB2805 • Rev. 1.0.3 31
FUSB2805 — USB2.0 High-Speed OTG Transceiver with ULPI Interface
No Automatic Generation of SYNC or EOP Packets
This functionality is considered optional in the ULPI
specification, but is supported by the FUSB2805 and
allows for the link to turn off the automatic generation of
SYNC and EOP packets. This is only pertinent to HS
packet data. It is provided for backward compatibility for
the controllers that include SYNC and EOP bytes in the
data payload when transmitting packets. The
FUSB2805 does not automatically generate SYNC and
EOP when OPMODE[1:0]=11b. The FUSB2805 NRZI
encodes the data and performs bit stuffing. The link
must always send packets using the TXCMD(NOPID)
packet type. The FUSB2805 does not provide bit
stuffing on an individual byte basis, but automatically
turns off bit stuffing for EOP when STP is asserted with
data set to FEh. If data is set to 00h when STP is
asserted, the FUSB2805 does not transmit an EOP.
The FUSB2805 also detects if the PID byte is A5h
(indicating SOF) and automatically sends a long EOP
when STP is asserted. To transmit chirp and resume
signaling, the link sets OPMODE[1:0]=10b.
Figure 19 shows USB packets without automatic SYNC
and EOP generation.
Please refer to ULPI specification, section 3.8.5.6 for
details on no SYNC and EOP generation functionality.
Idle
ULPI Signals
D [7:0]
STP
NXT
TxBitstuffEnable
DIR
USB Signals
TXCMD
TxValid
00h 00h 00h 08h PID D1
FEhDNDN-1
….
….
D3
D2
UTMI+ Equivalent Signals
TxReady
Idle Sync
PID
Data Payload
EOP
D+/D-
CLOCK
Figure 19. USB Packets without Automatic SYNC and EOP Generation (OpMode=11b)
OTG Operations
The FUSB2805 provides full support for OTG Rev. 1.3
compliance. The supporting functional blocks for dual-
role devices include:
 Voltage comparators (for V
BUS
-valid, session-end,
and session-valid signaling)
 DP and DM pull-up and pull-down resistors
compliant to the USB2.0 resistor ECN
 ID detection for micro-A or micro-B plug insertion
 V
BUS
charge and discharge resistors
V
BUS
Comparators
The FUSB2805 combines the A-device and B-device
session valid signals into V
SESS_VLD
due to overlapping
thresholds that allow for such combination.
The V
A_VBUS_VLD
threshold allows for the A-device to
determine if it is capable of outputting a valid voltage on
V
BUS
. For the FUSB2805, the V
BUS
source voltage is
external to the device when an A-device, so the
ExtV
BUS
Indicator signal must be utilized.
These comparators are controlled, and determine when
RXCMDs are sent, by interaction with the INTF_CTRL,
OTG_CTRL, USB_INTR_R, USB_INTR_F, USB_INTR_
STAT, and USB_INTR_L registers.
Table 13 defines use of the UseExternalVbusIndicator,
IndicatorPassThru, and IndicatorComplement register
bits to control the use of the ExternalVbusIndicator input
pin and the internal V
BUS
-valid comparator output to
generate the VA_VBUS_VLD indicator for encoding in
the RXCMD data byte.
Figure 20 shows a graphical representation of the
RXCMD V
BUS
-valid.