Datasheet

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FUSB2805 • Rev. 1.0.3 26
FUSB2805 — USB2.0 High-Speed OTG Transceiver with ULPI Interface
ULPI HOST
D0-D7
STP
NXT
K
TXCMD
NOPID
TXCMD
RegWr
K
SE0
TermSelect
OpMode
00
(Normal)
FS/LS
Detect
00
J K
J
…..
TXCMD
RegWr
00 (HS)
01 (FS)
XcvrSelect
USB Reset
10 (chirp)
00
(Normal)
LineState
J (01b)
SE0
(00b)
Peripheral Chirp-K
(10b)
Squelch
(00b)
Squelch
(00b)
Host Chirp-K/J
(10b/01b)
DIR
DIR
SE0
TXCMD
RegWr
K
TXCMD
NOPID
K K...
00
TXCMD
RegWr
00
K J
K J
K J
NXT
STP
RXCMDs
D0-D7
00 (HS)
01 (FS)
XcvrSelect
TermSelect
OpMode
00
(Normal)
10 (chirp)
00
(Normal)
LineState
J (01b)
SE0
(00b)
Peripheral Chirp-K
(10b)
Squelch
(00b)
Squelch
(00b)
Host Chirp-K/J
(10b/01b)
!Squelch
(01b)
Host
Drives
Peripheral
Responds
(chirp)
Host
Responds
(chirp)
HS
Idle
ULPI Peripheral
D+
D-
HS Detection Handshake (chirp)
USB Signals
t
0
Figure 14. USB Reset and HS Chirp Handshake Timing
Note:
17. Timing is not to scale and not all the RXCMD updates or bus turn-around cycles are necessarily shown. The bus
turn-around cycles would be included for one cycle after every assertion and de-assertion of DIR.