Datasheet

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FUSB2805 • Rev. 1.0.3 25
FUSB2805 — USB2.0 High-Speed OTG Transceiver with ULPI Interface
USB High-Speed Detection Handshake (Chirp)
The sequence for detection includes the USB reset and
the HS detection handshake (“chirp”) and includes the
following sequence of events:
1. USB Reset - The host detects the peripheral
attachment (LS if DM is HIGH; FS if DP is HIGH). If
LS is detected, the host does not continue with the
following sequence of events. If a FS peripheral is
detected, it resets the peripheral by writing to
FUNC_CTRL and setting XCVRSELECT[1:0]=00b
(high speed) and TERMSELECT=0b that drives a
SE0 on the bus (DP and DM connected to GND
through 45 Ω). The host also sets
OPMODE[1:0]=10b for correct chirp transmit and
receive. The start of SE0 is defined as T0 time. The
peripheral FUSB2805 asserts DIR and informs the
link of the LINESTATE change using an RXCMD.
Note:
16. The host must also take into account, when
receiving chirp signaling, the high-speed
differential receiver output so as not to see
false bus activity.
2. Peripheral Chirp Response - After detecting the
SE0 for no less than 2.5 µs; if HS capable, the
peripheral sets XCVRSELECT[1:0]=10b and
OPMODE[1:0]=10b, then sends immediately after a
TXCMD (NOPID) command. This means a
transmission of a chirp-K for no less than 1ms and
ending no more than 7 ms after the reset time, T0.
If the peripheral is in low-power mode, it must wake
up the clock within 5.6 ms, leaving 200 µs for the
link to start transmitting the chirp-K and 1.2 ms for
the chirp-K to complete (based on worst-case 10%
slow clock).
3. Host Chirp Response – If the host does not detect
the peripheral chirp, it must continue asserting SE0
until the end of reset. If the peripheral chirp
response is detected by the host for a period no
less than 2.5 µs, then no more than 100 µs after
the bus leaves chirp-K, the host sends a
TXCMD(NOPID) with an alternating sequence of
chirp-Ks and chirp-Js. Each chirp-K or chirp-J must
last no less than 40 µs and no longer than 60 µs.
4. High-Speed Idle Response – The peripheral must
detect a minimum of chirp K-J-K-J-K-J, with each
chirp detection being for at least 2.5 µs. The
peripheral sets TERMSELECT=0b and
OPMODE[1:0]=00b after seeing the minimum chirp
sequence. The peripheral is in high-speed mode
and detects the !squelch (LINESTATE=01b). When
the peripheral detects squelch (LINESTATE=10b),
it recognizes that the host has completed chirp and
waits for HS USB traffic to begin. After transmitting
the chirp sequence, the host changes
OPMODE[1:0]=00b and begins sending packets.
Figure 14 shows the USB reset and HS chirp sequence.
Refer to ULPI Rev. 1.1 specification, section 3.8.5.1 for
details on HS detection timing.