Datasheet
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FUSB2805 • Rev. 1.0.3 2
FUSB2805 — USB2.0 High-Speed OTG Transceiver with ULPI Interface
Block Diagram
ULP I
Interf ac e
Co ntro ller
Reg is ter
M ap
USB D ata
S erializer
USB D ata
D es erializer
USB 2.0 A TX
Term inatio n
Res is to rs
Fr eq uency
S elec t
P LL
V o ltag e
Reg ulato r
P o wer-O n
Res et
Global
Clo cks
P OR
ID D etec to r
OTG M odule
E xternal
VBUS
& Fault
D etec tio n
Co ntro l
B lo c k
A nalo g
Ref erence
M odule
Clo ck
D 0-D 7
D IR
S TP
NX T
CHIP _SELE CT_N
CF G 1
CLK IN
V IO
V CC3V 3
V CC1V 2
V CC
0.1 µF 4.7 µF
0.1 µF 4.7 µF
D P
D M
ID
VBUS
V
R E F
Res et_N
FA ULT
RRE F
PSW
100k
IC (Flo at)
Tes t (Flo at)
400k
50k
ID _P ULLUP
V
DD3 V 3
0.1 µF
Figure 1. Functional Block Diagram
Pin Configuration
GND
Exposed DiePad
1
2
3
4
5
6
7
8
D1
D0
VIO
DM
RREF
DP
VCC
ID
24
23
22
21
20
19
18
17
D2
CHIP_SELECT_N
D3
VIO
CGF1
CLOCK
D4
D5
32 31 252627282930
9 10 161514131211
D6
D7
NXT
STP
VIO
RESET_N
DIR
VDD1V2
VCC
TEST(FLOAT)
FAULT
VCC3V3
VBUS
PSW
CLIKIN
IC(FLOAT)
Figure 2. Pin Assignments (Through View)