Datasheet

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FUSB2805 • Rev. 1.0.3 19
FUSB2805 — USB2.0 High-Speed OTG Transceiver with ULPI Interface
CLOCK
D0-D7
STP
DIR
NXT
D0TXCMD
DATA
D1
TX End Delay ( 2 to 5 clocks)
D
N-1
D
N
EOP
DP or
DM
IDLE
SYNC
Link Decision Time (15 to 24 clocks)
TX Start Delay
(1 to 2 clocks)
USB Inter Packet Delay (88 to 192 HS bit times)
Figure 12. HS Transmit to Transmit Packet Timing, Example 2
Preamble
Preamble packets are headers to low-speed packets
that must travel over a FS bus between a host and a
hub. To enter preamble mode, the link sets
XCVRSELECT[1:0]=11b in the FUNC_CTRL register
and, when in this mode (Preamble), the FUSB2805
operates just as in FS mode and sends all the data with
the FS rise and fall time characteristics. Whenever the
link transmits a USB packet in preamble mode, the
FUSB2805 automatically sends a preamble header at
the FS bit rate before sending the packet at low-speed
bit rate. The FUSB2805 ensures a minimum gap of four
FS bit times between the last bit of the FS PRE_PID
and the first bit of the LS SYNC. The FUSB2805 drives
a J-state for at least one FS bit time after sending the
PRE-PID, after which the resistor can hold the J-state
on the bus. In preamble mode, the FUSB2805 can also
receive LS packets from the FS bus. Figure 13 shows
an example preamble packet.
CLOCK
D0-D7
STP
DIR
NXT
D0TXCMD (LS PID)
D1
LS D1
DP or
DM
LS D0LS PID
LS
SYNC
IDLE
(4 FS bits
min)
FS
PRE_ID
FS
SYNC
Figure 13. Preamble Sequence