Datasheet
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FUSB2805 • Rev. 1.0.3 10
FUSB2805 — USB2.0 High-Speed OTG Transceiver with ULPI Interface
ULPI Signals
D [7:0]
STP
NXT
DIR
TXCMD
RegWr
SuspendM
Data
Turn
Around
CLOCK
Low Power Mode Signals
t
CS
t
STP
1
Note: The second STP pulse indicates the exit of low-power (suspend) mode
Figure 6. Entering Low-Power Mode
Exiting Low-Power Mode
If the FUSB2805 has been in suspend at least 2 µs, the
link may signal the FUSB2805 to exit low-power mode
by asynchronously asserting STP. The FUSB2805
immediately starts to wake up its internal circuitry. Upon
meeting the ULPI timing requirements the FUSB2805
then de-asserts DIR, ensuring a minimum of 5 cycles of
CLOCK have been driven before de-asserting DIR and
setting SuspendM=1b (in Function Control Register).
The link de-asserts STP in the cycle following the de-
assertion of DIR. There is one cycle of data bus
turnaround provided after the assertion of DIR, during
which the value of D[7:0] is not valid. Upon completion
of the turnaround cycle the FUSB2805 begins driving
the signals as described in Table 1.
ULPI Signals
D [7:0]
STP
NXT
DIR
SuspendM
Turn
Around
PHY Output CLOCK
Synchronous Mode Signals
Low-Power Mode Signals
t
WU
t
CWU
t
CD
Figure 7. Exiting Low-Power Mode when FUSB2805 Provides Output CLOCK
6-Pin Full-Speed / Low-Speed Serial Mode
This mode of operation is provided for links that contain
legacy FS/LS functionality and enables a cost-effective
upgrade path to HS functionality.
To enter 6-pin serial mode, the link controller sets the
6PIN_FSLS_SERIAL bit in the interface control register
to logic 1. To exit 6-pin serial mode, the link controller
asserts STP.
An INT signal is also provided to inform the link of USB
events. If the link requires CLOCK to be running during 6-
pin serial mode, the CLK_SUSPENDM register bit must
be set to logic 1b before entering 6-pin serial mode.
The FUSB2805 requires CLKIN to be kept running when
in 6-pin mode. In 6-pin serial mode, the data bus
assignments are changed to those described in Table
2. Examples of the signaling of data packets are shown
in Figure 22.