FUSB2805 USB2.0 High-Speed OTG Transceiver with ULPI Interface Features Description Complies with USB 2.0, OTG Rev 1.3 Supplement, and ULPI Rev 1.1 Specifications Supports 480 Mbps, 12 Mbps, and 1.5 Mbps USB2.0 Speeds The FUSB2805 is a UTMI+ Low-Pin Interface (ULPI) USB2.0 OTG transceiver. It is compliant with the Universal Serial Bus Specification Rev 2.0 (USB2.0), the ULPI Specification Rev. 1.1, and the On-The-Go (OTG) supplement to USB2.0, Rev. 1.3.
Clo c k D 0-D 7 D IR S TP NX T ULP I Interf ac e Co ntro ller US B D ata S erializer US B 2.0 A TX DP Reg is ter M ap US B D ata D es erializer Term inatio n Res is to rs DM CHIP _S E LE CT_N V D D 3V3 ID _P ULLUP G lo b al Clo c ks P LL 50k O TG M o d ule F req uenc y S elec t 400k CF G 1 ID ID D etec to r CLK IN V B US V IO 0.1µF Res et_N V CC3V 3 0.1µF POR P o wer-O n Res et 4.7µF E x ternal V B US & F ault D etec tio n Co ntro l B lo c k V CC1V 2 0.1µF 4.
Symbol Type (1) Description Active LOW. HIGH – ULPI pin three-stated; LOW – ULPI operates normally. TTL compatible; CMOS input with hysteresis. Chip Select_N I RREF AI/O Resistor reference. Connect through 12 k 1% to GND. DM AI/O USB D- pin. USB mode: data minus (D-) pin of the USB cable. DP AI/O USB D+ pin. USB mode: data plus (D+) pin of the USB cable. FAULT I FAULT is used to signal a VBUS over-current/over-voltage condition from an external SMPS or power management IC.
ULPI Interface Controller USB 2.0 ATX The FUSB2805 provides a 12-pin interface (SDR) compliant with the UTMI+ Low-Pin Interface (ULPI) specification, revision 1.1. This interface must be connected to the USB link controller. The USB 2.0 ATX block is an analog front-end containing the circuitry needed for transmitting, receiving, and terminating the USB bus in high speed (HS), full speed (FS), and low speed (LS); for USB peripheral, host, and OTG implementations; per the USB2.
3-State (ignored) CLOCK Chip_Select_N D[7:0] 3-State (input) 3-State (ignored) STP 3-State (input) 3-State (ignored) NXT 3-State DIR 3-State Figure 3. ULPI Behavior with Chip_Select_N as a Power-Down Control Signal (active HIGH reset) in the USB OTG PHY block must remain asserted for no less than 40 µs. Power Down Using Chip_Select When CHIP SELECT_N is de-asserted (HIGH), the FUSB2805 three-states the ULPI interface pins and powers down the internal circuitry.
Session-Valid Comparator The session-valid comparator is a TTL-level input that determines when VBUS is high enough for a session to start. Both the A-device and the B-device use this comparator to detect when a session is being started. The A-device also uses this comparator to determine when a session is completed. The session valid threshold is between 0.8 V to 2.0 V. The OTG module contains several sub-blocks that provide the functionality required by the USB On-TheGo Rev. 1.3 supplement.
D0 to D7 RREF D0 to D7 are bi-directional ULPI data bus pins. The USB link controller must drive D0-D7 LOW when the ULPI bus is idle (DIR is LOW). When the link has data to transmit to the FUSB2805, it drives a non-zero value. Resistor reference analog I/O pin. A 12 k 1% resistor is required. The data bus can be re-configured to carry different data types. There are four modes of the data bus: When in USB mode, the DP pin functions as USB data plus line; the DM pin functions as USB data minus line.
IR VCC is the main input supply voltage for FUSB2805. The FUSB2805 operates correctly when VCC is between 2.7 V and 4.5 V. The maximum transients that should be seen on VCC are 5.5V for a maximum of 5ms. A 100nF decoupling capacitor is preferred. Direction output pin. This pin is synchronous to the rising edge of CLOCK and controls the direction of the data bus. By default, the FUSB2805 holds DIR LOW, causing the data bus to be an input.
ULPI Modes Low-Power Mode The ULPI bus can be programmed to operate in four different modes and a power-down mode. Each mode re-configures the signals on the data bus. Setting more than one mode leads to undefined behavior. When the USB is idle, the link controller can place the FUSB2805 into low-power mode (also known as “suspend” mode). To enter low-power mode, the link controller clears the SUSPENDM bit in the function control (FUNC_CTRL) register to 0b.
CLOCK D [7:0] TXCMD RegWr Turn Around Data Low Power Mode Signals DIR tCS tSTP1 STP NXT SuspendM Note: The second STP pulse indicates the exit of low-power (suspend) mode Figure 6. Entering Low-Power Mode Exiting Low-Power Mode If the FUSB2805 has been in suspend at least 2 µs, the link may signal the FUSB2805 to exit low-power mode by asynchronously asserting STP. The FUSB2805 immediately starts to wake up its internal circuitry.
Signal Mapping on ULPI Bus During 6-Pin Serial Mode Signal Maps To Direction Description TX_ENABLE D0 In Active-HIGH transmit enable TX_DATA D1 In Transmit the differential data on DP and DM TX_SE0 D2 In Transmit single-ended zero (SE0) on DP and DM INT D3 Out Active-HIGH interrupt signal; asserted and latched whenever any unmasked interrupt occurs RX_DP D4 Out Single-ended receive data from DP RX_DM D5 Out Single-ended receive data from DM RX_RCV D6 Out Differential receive d
A high-speed USB host or On-The-Go (OTG) device handles more than one electrical state, as defined in the USB and OTG specifications. The FUSB2805 accommodates the various states through the register Table 4. bit settings of XcvrSelect, TermSelect, OpMode[1:0], DpPulldown, and DmPulldown. Table 4 summarizes the operating states.
ULPI References ULPI Bus The FUSB2805 provides a 12-pin (SDR) ULPI interface for communication with the link controller. It is strongly recommended that users of the FUSB2805 read the ULPI and UTMI+ specifications as listed below: A description of the ULPI pin signals are given in Table 5. During synchronous mode, all signals are synchronous to CLOCK. Using the ULPI bus, the link controller can perform register reads and writes and transmit data on the USB bus.
FUSB2805 accepts TXCMD Link sends next data. FUSB2805 accepts Link signals end of data ULPI bus is idle FUSB2805 asserts DIR, causing turnaround cycle FUSB2805 sends RXCMD (NXT low) FUSB2805 FUSB2805 sends USB de-asserts DIR, data causing (NXT high) turnaround cycle CLOCK D0-D7 TXCMD Turn around DATA RXCMD DATA Turn around DIR STP NXT Figure 8.
V IO Chip_Select_N Regulator Powerup Powerup t PWRUP Bus Idle Internal PORB CLKIN tstartPLL Clock (output) Internal clock stable Reset Command Clock Start D[7:0] TXCMD DATA Internal reset RXCMD Update DIR STP NXT t1 t2 t3 t4 t5 t6 Figure 9. Power-up, Reset, and Bus Idle Sequence for ULPI Ready Notes: 4. With the CLKIN stable, the FUSB2805 drives a 60 MHz clock out from the CLOCK pin when DIR de-asserts. This is shown as “CLOCK (output)” above. 5. t1: VCC is applied to the FUSB2805. 6.
When transmitting and receiving USB packets, there are limits set on the link and PHY processing time to ensure that USB inter-packet delays are also met. Link sends TXCMD FUSB2500 accepts TXCMD Link sends next data. FUSB2500 accepts. These times are determined by the USB event and the packet format (i.e. transmit with PID or NOPID, transmit error, receive error, etc.).
The USB2.0 specification defines the inter-packet timing and the UTMI/UTMI+ specifications define synchronization and processing delays. The ULPI Rev. 1.1 specification defines the inter-packet delays to ensure compatibility with USB2.0 and supplemental specifications. Table 6. Pipeline Delays Table 6 describes the delays (in clock cycles) with which to comply using ULPI. The USB bus events are measured relative to D+ and D-.
Table 7. Link Decision Times HS PHY FS PHY LS PHY Delay Delay Delay Parameter Name Definition Number of clocks a host link must wait before driving the TXCMD for the second packet. Transmit-Transmit (Host Only) 15 to 24 7 to 18 77 to 247 In HS, the link starts counting from the assertion of STP for the first packet. In FS, the link starts counting from the RXCMD indicating LINESTATE has transitioned from SE0-to-J for the first packet. The timings given ensure inter-packet delays of 2.0 to 6.
DP or DM EOP DATA SYNC IDLE CLOCK D0-D7 DN-1 TXCMD DN D0 D1 DIR STP NXT TX End Delay ( 2 to 5 clocks) Figure 12. Link Decision Time (15 to 24 clocks) HS Transmit to Transmit Packet Timing, Example 2 the FS bit rate before sending the packet at low-speed bit rate. The FUSB2805 ensures a minimum gap of four FS bit times between the last bit of the FS PRE_PID and the first bit of the LS SYNC.
ULPI modifies the original UTMI data stream such that it can fit more data types. Redundancy in the PID byte during transmit is overloaded with ULPI transmit commands (TXCMD). Unused data bytes in the receive stream are overloaded with receive commands (RXCMD). ULPI defines a transmit command byte that is sent by the link and a receive command byte that is sent by the FUSB2805. Table 8.
The FUSB2805, after asserting DIR, uses the receive command (RXCMD) byte to update the link on line state, USB receive, disconnect, and OTG information via the ULPI data bus. Table 9. RXCMD Data Byte Format DATA[7:0] Status Name Description Line State Signals: D[0]: LINESTATE0 [1:0] LINESTATE D[1]: LINESTATE1 LINESTATE[1:0] reflects the current status of DP and DM and is a function of various register settings and whether the device is a host or peripheral.
As mentioned in Table 9, the LINESTATE[1:0] sent to the link is a function of whether the port is upstream (peripheral) or downstream (host) facing. Dual-role OTG devices must select the correct LINESTATE encoding, depending upon its mode. Note that the configuration as a LS peripheral (upstream facing port), with DM pullup, is not supported by the FUSB2805. Table 10.
As mentioned in Table 9, changes in the VBUS state encoding initiate an RXCMD to the link. For the link to receive VBUS state updates, the link must first enable the corresponding interrupts in the USB_INTR_EN_R and USB_INTR_EN_F registers. Link uses the indicator signals to take action based on typical configurations (host, peripheral, OTG device). Table 12 shows the VBUS indicators in RXCMD based on the configuration.
The link can read or write register bytes, and set or clear register bits as needed, using the TXCMD byte. The FUSB2805 supports immediate and extended addressing register operations, with the extended register addressing being optional for the link. If the FUSB2805 asserts DIR during an operation, the register operation is aborted. When a register operation is aborted, the link must retry until successful.
The sequence for detection includes the USB reset and the HS detection handshake (“chirp”) and includes the following sequence of events: 1. USB Reset - The host detects the peripheral attachment (LS if DM is HIGH; FS if DP is HIGH). If LS is detected, the host does not continue with the following sequence of events.
HS Detection Handshake (chirp) USB Reset FS/LS Detect TXCMD RegWr D0-D7 Host Drives t0 Host Responds (chirp) Peripheral Responds (chirp) SE0 00 K TXCMD NOPID K J ….. HS Idle K TXCMD RegWr J DIR NXT STP XcvrSelect 01 (FS) 00 (HS) TermSelect OpMode 00 (Normal) LineState 00 (Normal) 10 (chirp) Squelch (00b) Peripheral Chirp-K (10b) SE0 (00b) J (01b) Host Chirp-K/J (10b/01b) Squelch (00b) ULPI Peripheral RXCMDs SE0 TXCMD RegWr D0-D7 TXCMD NOPID K K ...
This section describes the suspend and resume functionality, when initiated by a host or hub, and how to subsequently wake the downstream peripheral. clearing the SUSPENDM bit in the FUNC_CTRL register, causing the FUSB2805 to draw only suspend current. The host may or may not be powered down. Full-Speed Suspend and Resume 3. Resume K – When the host wishes to wake the peripheral, it sets OPMODE[1:0]=10b and transmits a K-state for at least 20 ms.
The sequence of events for a host and HS peripheral using FUSB2805 is described below and shown in Figure 16. FUNC_CTRL register, causing the FUSB2805 to draw only suspend current. The host also changes the FUSB2805 to FS mode (XCVRSELECT[1:0]=01b), removes the 45 Ω terminations (TERMSELECT=1b), and may or may not be powered down. Sequence of events: 1. 2. HS Traffic – Initially both the host and peripheral are idle.
The FUSB2805 supports peripherals that can initiate remote wake-up. When placed into USB suspend, the peripheral remembers the speed at which it was originally operating. Depending on that original operating speed, the link follows one of the protocols described below. The sequence of events is: 1. Both the host and peripheral are assumed to be in low-power mode. 2. The peripheral begins remote wake-up by re-enabling the clock and setting its SUSPENDM bit=1b. 3.
signaling in response to the remote wake-up event. This can be viewed as a „light sleep‟ mode whereby the PHY is suspended, internal PLL and clock trees are powered down, but power is being dissipated in the system to run CLKIN. If, however, the implementation is such that the CLKIN is also powered down, it is most likely to take >1 ms to wake from suspended (low-power) mode.
This functionality is considered optional in the ULPI specification, but is supported by the FUSB2805 and allows for the link to turn off the automatic generation of SYNC and EOP packets. This is only pertinent to HS packet data. It is provided for backward compatibility for the controllers that include SYNC and EOP bytes in the data payload when transmitting packets. The FUSB2805 does not automatically generate SYNC and EOP when OPMODE[1:0]=11b. The FUSB2805 NRZI encodes the data and performs bit stuffing.
Please refer to ULPI specifications, section 3.8.7, for details on OTG functionality with respect to ULPI or OTG supplement Rev. 1.3 for USB2.0. Please refer to ULPI specifications section 3.8.7.3 for further detail on OTG VBUS comparator thresholds. Table 13.
Figure 21 and Figure 22 provide examples of 6-pin and 3-pin serial modes as controlled in the INTF_CTRL register via the 6-pin and 3-pin register bits. Please refer to ULPI specification, section 3.10 for details on the 3-pin and 6-pin serial mode functionality. TRANSMIT RECEIVE DATA[0] Tx_Enable SYNC DATA EOP SYNC DATA EOP DATA[1] Tx_DAT/ RX_RCV DATA[2] Tx_SE0/ RX_SE0 DP DM Figure 21.
ULPI provides an immediate register set, with a 6-bit address, that is part of the transmit command byte. An extended register set is also provided (8-bit address) that requires an extra clock cycle to complete. The immediate register set is mirrored into the lower end of the extended address space. For example, an operation to the extended address of 00XXXXXX operates on the immediate register set. The FUSB2805 must support both immediate and extended register operations.
Table 16. Vendor ID and Product ID Registers Register Bits Access Address Value Description VENDOR_ID_LOW 7:0 rd 00h 79h Lower byte of vendor ID supplied by USB-IF. Fixed value of 79h. VENDOR_ID_HIGH 7:0 rd 01h 07h Upper byte of vendor ID supplied by USB-IF. Fixed value of 07h. PRODUCT_ID_LOW 7:0 rd 02h 00h Lower byte of product ID number. Fixed value of 00h. PRODUCT_ID_HIGH 7:0 rd 03h 25h Upper byte of product ID number. Fixed value of 25h.
These registers control various interface and PHY features of the FUSB2805. All bits in this register are viewed as optional features in the ULPI Specification Rev 1.1; however, many are supported by the FUSB2805 and are provided for legacy link cores. Table 18. Interface Control Register Field Name 6-pin FsLsSerialMode 6PIN_FSLS_SER Bits Access Reset 0 rd/wr/s/c Description 0b Changes the ULPI interface to 6-pin serial mode.
Bits Interface Protect Disable INTF_PROT_DIS 7 Access rd/wr/s/c Reset 0b Description Controls circuitry built into the FUSB2805 for protecting the ULPI interface when the link three-states STP and D[7:0]. Any pull-ups or pull-downs employed by this feature can be disabled. This bit is not intended to affect the operation of the holding state. When this bit is enabled, the FUSB2805 automatically detects when the link stops driving STP. 0b: Enables the interface-protect circuit (default).
These register bits control the interrupt event notification settings of the FUSB2805 for LOW-to-HIGH signal changes. By default, all transitions are enabled. Interrupt circuitry can be powered down in any mode when both rising and falling edge enables are disabled. To ensure interrupts are detectable when CLOCK is powered down, the link should enable both rising and falling edges. Table 20.
These register bits indicate the current value of the interrupt event source signal. Interrupt circuitry can be powered down in any mode when both rising and falling edge enables are disabled. To ensure interrupts are detectable when CLOCK is powered down, the link should enable both rising and falling edges. Table 22. USB Interrupt Status Register Field Name Bits Access Reset HostDisconnect 0 rd 0b Current value of UTMI+ HostDisconnect output.
USB interrupt latch bit is set, the interrupt condition is given immediately in the register read data and the latch bit is not set to 1b. Table 24.
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter (25) VCC Supply Voltage VIO I/O Supply Voltage VIN DC Input Voltage (26) Min. Max.
VCC3V3=VCC-0.1 to 3.6 V; VDD1V2=1.1 V to 1.25 V; VIO=1.65 V to 3.60 V; TJ=-40°C to +85°C; unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit 1.
VCC3V3=VCC-0.1 to 3.6 V; VDD1V2=1.1 V to 1.25 V; VIO=1.65 V to 3.60 V; TJ=-40°C to +85°C; unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit 0.2 V 2.5 V 0.8 V Analog I/O Pins (DP, DM) FS/LS Path VDI Differential Input Sensitivity |VDP – VDM| VCM Differential Common Mode Voltage Includes VDI Range VIL LOW-Level Input Voltage VIH HIGH-Level Input Voltage VOL LOW-Level Output Voltage Pull-Up on DP; RL=1.5 k to 3.
VCC3V3= VCC-0.1 to 3.6 V; VDD1V2=1.1 V to 1.25 V; VIO=1.65 V to 3.60 V; TJ=-40°C to +85°C; unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max.
VCC3V3= VCC-0.1 to 3.6 V; VDD1V2=1.1 V to 1.25 V; VIO=1.65 V to 3.60 V; TJ=-40°C to +85°C; unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit Output CLOCK Characteristics Active Only When a Clock is Input on CLKIN fCLK60_OUT Output Clock Frequency 60 MHz JCLK60_OUT RMS Output Jitter CLK60_OUT Duty Cycle tR_CLK60 Rise Time CLOCK Pin Transitioning from 10% to 90% of VIO (CL – 4-12 pF) 1.0 4.
VCC3V3= VCC-0.1 to 3.6 V; VDD1V2=1.1 V to 1.25 V; VIO=1.65 V to 3.60 V; TJ=-40°C to +85°C; unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit ULPI Interface Exiting and Entering Low-Power Mode From DIR LH Transition-to-CLOCK Stop (6 Cycles Minimum) 0.
VCC3V3= VCC-0.1 to 3.6 V; VDD1V2=1.1 V to 1.25 V; VIO=1.65 V to 1.95 V; TJ=-40°C to +85°C; unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max.
5.25 MIN (3.75) 0.15 C 3.10 MAX 5.10 4.90 (2X) B (0.60 ) A (0.48 ) 5.25 MIN 5.10 4.90 3.10 MAX (3.75 ) PIN #1 IDENT (0.21 ) X4 0.15 C (2X) TOP VIEW 0.28 MAX X32 0.50 RECOMMENDED LAND PATTERN 0.80 MAX 0.10 C (0.20) 32X 0.08 C 0.05 0.00 SEATING PLANE C SIDE VIEW NOTES: A. EXCEPT WHERE NOTED, CONFORMS TO JEDEC REGISTRATION MO-220, VARIATION WHHD-6. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994. D. LAND PATTERN PER IPC SM-782. E.
FUSB2805 — USB2.0 High-Speed OTG Transceiver with ULPI Interface © 2008 Fairchild Semiconductor Corporation FUSB2805 • Rev. 1.0.3 www.fairchildsemi.
