Datasheet

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May 2001

Revised June 2005

FSTD16861 20-Bit Bus Switch with Level Shifting

FSTD16861

20-Bit Bus Switch with Level Shifting

General Description

The Fairchild Switch FSTD16861 provides 20-bits of high-

speed CMOS TTL-compatible bus switching. The low On

Resistance of the switch allows inputs to be connected to

outputs without adding propagation delay or generating

additional ground bounce noise. A diode to V

has been

integrated into the circuit to allow for level shifting between

5V inputs and 3.3V outputs.

The device is organized as a 10-bit or 20-bit bus switch.

When OE

is LOW, the switch is ON and Port 1A is con-

nected to Port 1B. When OE

is LOW, Port 2A is connected

to Port 2B. When OE

is HIGH, a high impedance state

exists between the A and B Ports.

Features

■ 4 switch connection between two ports.

■ Minimal propagation delay through the switch.

■ Low l

■ Zero bounce in flow-through mode.

■ Control inputs compatible with TTL level.

■ TruTranslation voltage translation from 5.0V inputs to

3.3V outputs

■ Power-off high impedance inputs and outputs

■ Supports live insertion/withdrawal (Note 1)

Note 1: To ensure the high-impedance state during power up or power

down, OE

should be tied to V

through a pull-up resistor; the minimum

value of the resistor is determined by the current-sourcing capability of the

driver.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

TruTranslation

is trademark of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

FSTD16861MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Summary of content (6 pages)

PAGE 1
Revised June 2005 FSTD16861 20-Bit Bus Switch with Level Shifting General Description Features The Fairchild Switch FSTD16861 provides 20-bits of highspeed CMOS TTL-compatible bus switching. The low On Resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. A diode to VCC has been integrated into the circuit to allow for level shifting between 5V inputs and 3.3V outputs. ■ 4: switch connection between two ports.
PAGE 2
FSTD16861 Connection Diagram Logic Diagram Pin Descriptions Truth Table Pin Name Description OE1, OE2 Bus Switch Enables OE1 Inputs OE2 Inputs/Outputs 1An, 2An Bus A L L 1A 1B 1Bn, 2Bn Bus B L H 1A 1B H L Z H H Z H HIGH Voltage Level L LOW Voltage Level Z High Impedance www.fairchildsemi.
PAGE 3
Supply Voltage (VCC) DC Switch Voltage (VS) (Note 3) DC Input Voltage (VIN) (Note 4) DC Input Diode Current (lIK) VIN 0V Recommended Operating Conditions (Note 5) 0.5V to 7.0V 0.5V to 7.0V 0.5V to 7.0V 50 mA DC Output Current (IOUT) 128 mA DC VCC/GND Current (ICC/IGND) Storage Temperature Range (TSTG) 4.5V to 5.5V Power Supply Operating (VCC) Input Voltage (VIN) 0V to 5.5V Output Voltage (VOUT) 0V to 5.
PAGE 4
FSTD16861 AC Electrical Characteristics TA Symbol Parameter CL 40 qC to 85 qC, 50pF, RU VCC Min tPHL, tPLH Propagation Delay Bus-to-Bus (Note 8) tPZH, tPZL Output Enable Time tPHZ, tPLZ RD Units Figure Conditions Number Max 0.25 ns 6.0 ns 1.0 Output Disable Time 500: 4.5 – 5.5V 1.0 7.0 ns VI OPEN Figures 1, 2 Figures 1, 2 VI 7V for tPZL VI OPEN for tPZH VI 7V for tPLZ VI OPEN for tPHZ Figures 1, 2 Note 8: This parameter is guaranteed by design but is not tested.
PAGE 5
FSTD16861 Output Voltage HIGH vs. Supply Voltage FIGURE 3. 5 www.fairchildsemi.
PAGE 6
FSTD16861 20-Bit Bus Switch with Level Shifting Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Technology Description The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its 74LVX3L384(FST3384) bus switch product.