Datasheet

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June 2000

Revised April 2005

FSTD16211 24-Bit Bus Switch with Level Shifting

FSTD16211

24-Bit Bus Switch with Level Shifting

General Description

The Fairchild Switch FSTD16211 provides 24-bits of high-

speed CMOS TTL-compatible bus switching. The low On

Resistance of the switch allows inputs to be connected to

outputs without adding propagation delay or generating

additional ground bounce noise. A diode to V

has been

integrated into the circuit to allow for level shifting between

5V inputs and 3.3V outputs.

The device is organized as a 12-bit or 24-bit bus switch.

When OE

is LOW, the switch is ON and Port 1A is con-

nected to Port 1B. When OE

is LOW, Port 2A is connected

to Port 2B. When OE

1/2

is HIGH, a high impedance state

exists between the A and B Ports.

Features

■ 4 switch connection between two ports

■ Voltage level shifting

■ Minimal propagation delay through the switch

■ Low l

■ Zero bounce in flow-through mode

■ Control inputs compatible with TTL level

■ Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Ordering Code:

Note 1: Ordering code “G” indicates Trays.

Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Diagram

Order Number Package Number Package Description

FSTD16211G

(Note 1)(Note 2)

BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

FSTD16211MTD

(Note 2)

MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Summary of content (7 pages)

PAGE 1
Revised April 2005 FSTD16211 24-Bit Bus Switch with Level Shifting General Description Features The Fairchild Switch FSTD16211 provides 24-bits of highspeed CMOS TTL-compatible bus switching. The low On Resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. A diode to VCC has been integrated into the circuit to allow for level shifting between 5V inputs and 3.3V outputs.
PAGE 2
FSTD16211 Connection Diagrams Pin Descriptions Pin Assignment for TSSOP Pin Name Description OE1, OE2 Bus Switch Enables 1A, 2A Bus A 1B, 2B Bus B NC No Connect Pin Assignment for FBGA 1 2 3 4 5 6 A 1A2 1A1 NC OE2 1B1 1B2 B 1A4 1A3 1A7 OE1 1B3 1B4 C 1A6 1A5 GND 1B7 1B5 1B6 D 1A10 1A9 1A8 1B8 1B9 1B10 E 1A12 1A11 2A1 2B1 1B11 1B12 F 2A4 2A3 2A2 2B2 2B3 2B4 G 2A6 2A5 VCC GND 2B5 2B6 H 2A8 2A7 2A9 2B9 2B7 2B8 J 2A12 2A11 2A10 2B10
PAGE 3
Recommended Operating Conditions (Note 6) 0.5V to 7.0V 0.5V to 7.0V 0.5V to 7.0V 50 mA Supply Voltage (VCC) DC Switch Voltage (VS) (Note 4) DC Input Control Pin Voltage (VIN)(Note 5) DC Input Diode Current (lIK) VIN 0V DC Output (IOUT) 128 mA DC VCC/GND Current (ICC/IGND) Storage Temperature Range (TSTG) 4.5V to 5.5V Power Supply Operating (VCC) Input Voltage (VIN) 0V to 5.5V Output Voltage (VOUT) 0V to 5.
PAGE 4
FSTD16211 AC Electrical Characteristics TA Symbol Parameter CL 40 qC to 85 qC, 50pF, RU VCC RD Min tPHL, tPLH Propagation Delay Bus to Bus (Note 9) tPZH, tPZL Output Enable Time tPHZ, tPLZ Units Figure Conditions Number Max 0.25 ns VI OPEN Figures 1, 2 5.5 ns VI 7V for tPZL VI OPEN for tPZH Figures 1, 2 VI 7V for tPLZ VI OPEN for tPHZ 1.5 Output Disable Time 500: 4.5 – 5.5V 1.5 6.5 ns Figures 1, 2 Note 9: This parameter is guaranteed by design but is not tested.
PAGE 5
FSTD16211 Output Voltage HIGH vs. Supply Voltage FIGURE 3. 5 www.fairchildsemi.
PAGE 6
FSTD16211 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A www.fairchildsemi.
PAGE 7
FSTD16211 24-Bit Bus Switch with Level Shifting Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Technology Description The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its 74LVX3L384 (FST3384) bus switch product.