Datasheet

12 www.fairchildsemi.com
FSBB30CH60C Rev. D
FSBB30CH60C Smart Power Module
Note:
1) RC coupling at each input might change depending on the PWM control scheme used in the application and the wiring impedance of the application’s printed circuit board. The
SPM input signal section integrates 5k
Ω (typ.) pull-down resistor. Therefore, when using an external filtering resistor, please pay attention to the signal voltage drop at input ter-
minal.
2) The logic input is compatible with standard CMOS or LSTTL outputs.
Figure 11. Recommended CPU I/O Interface Circuit
Note:
1) The ceramic capacitor placed between V
CC
-COM should be over 1uF and mounted as close to the pins of the SPM as possible.
Figure 12. Recommended Bootstrap Operation Circuit and Parameters
CPU
COM
5V-Line
,,
IN
(UL)
IN
(VL)
IN
(WL)
,,
IN
(UH)
IN
(VH)
IN
(WH)
V
FO
1nF
SPM
C
PF
= 1nF
R
PF
=4.7㏀
100Ω
100Ω
1nF 1nF
100Ω
15V-Line
22uF
0.1uF
1000uF 1uF
One-Leg Diagram of SPM
Inverter
Output
P
N
These Values depend on PWM Control Algorithm
Vcc
IN
COM
VB
HO
VS
Vcc
IN
COM
OUT
V
SL