Datasheet

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FSA2267/FSA2267A 0.35 Low-Voltage Dual-SPDT Analog Switch

March 2012

FSA2267 / FSA2267A Rev. 1.0.5

FSA2267 / FSA2267A

0.35 Low-Voltage Dual-SPDT Analog Switch

Features

•

Typical 0.35 On Resistance (R

) for +2.7V Supply

•

FSA2267A Features <10µA I

CCT

Current

when S Input is Lower than V

•

Fatness for +2.7V Supply: 0.25 Maximum

•

1.6mm x 2.1mm 10-Lead MicroPak™ Package

•

Broad V

Operating Range

•

Low THD (0.02% Typical for 32Load)

•

High Current Handling Capability (350mA Continuous

Current <3.3V Supply)

Applications

•

Cell phone

•

PDA

•

Portable Media Player

Description

The FSA2267 and FSA2267A are Dual Single Pole Dou-

ble Throw (SPDT) analog switches. The FSA2267 oper-

ates from a single 1.65V to 3.6V supply, while the

FSA2267A operates from a single 2.3V to 4.3V supply.

Each features an ultra-low On Resistance of 0.35 at a

+2.7V supply and 25°C. Both devices are fabricated with

sub-micron CMOS technology to achieve fast switching

speeds and designed for break-before-make operation.

FSA2267A features very low quiescent current, even

when the control voltage is lower than the V

supply.

This feature services the mobile handset applications

very well, allowing for the direct interface with baseband

processor general-purpose I/Os.

Ordering Information

Figure 1. Application Diagram

Order Number Top Mark Package Description Packing Method

FSA2267L10X FC 10-Lead MicroPak, 1.6 x 2.1mm, JEDEC MO-255

5000 Units on Tape

and Reel

FSA2267AL10X FD 10-Lead MicroPak, 1.6 x 2.1mm, JEDEC MO-255

5000 Units on Tape

and Reel

FSA2267AMUX

FSA

2267A

10-Lead Molded Small Outline Package (MSOP),

JEDEC MO-187, 3.0mm Wide

4000 Units on Tape

and Reel

Summary of content (14 pages)

PAGE 1
FSA2267 / FSA2267A 0.35 Low-Voltage Dual-SPDT Analog Switch Features Description • The FSA2267 and FSA2267A are Dual Single Pole Double Throw (SPDT) analog switches. The FSA2267 operates from a single 1.65V to 3.6V supply, while the FSA2267A operates from a single 2.3V to 4.3V supply. Each features an ultra-low On Resistance of 0.35 at a +2.7V supply and 25°C. Both devices are fabricated with sub-micron CMOS technology to achieve fast switching speeds and designed for break-before-make operation.
PAGE 2
FSA2267/FSA2267A 0.35 Low-Voltage Dual-SPDT Analog Switch Analog Symbols 1B0 1B1 1A 1S 2B0 2B1 2A 2S Figure 2. Analog Symbol Connections Diagram Vcc 1B0 1 10 Vcc 1B1 2 9 1A 2B0 3 8 1S 2B1 4 7 2S GND 5 6 2A 10 9 1A 2 8 1S 2B0 3 7 2S 2B1 4 6 2A 1B0 1 1B1 5 GND Figure 4. 10-Lead Micropak Figure 3.
PAGE 3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.. Symbol Parameter Min. Max. Unit Supply Voltage -0.5 +5.5 V VS Switch Voltage(1) -0.5 VCC + 0.
PAGE 4
ESD Performance of the FSA2267/FSA2267A FSA2267 ? HBM all pins 7.0kV ? CDM all pins 1.0kV FSA2267A HBM all pins 7.5kV ? CDM all pins 1.0kV ? Figure 5. Human Body ESD Test Model Human Body Model Figure 5 shows the schematic representation of the Human Body Model ESD event. Figure 6 is the ideal waveform representation of the Human Body Model. The device is tested to JEDEC: JESD22-A114 Human Body Model.
PAGE 5
All typical values are at 25°C unless otherwise specified. Symbol Parameter VCC Conditions (V) VIH VIL IIN Input Voltage High Input Voltage Low Control Input Leakage INO(OFF), Off-Leakage Current of INC(OFF) Port nB0 and nB1 IA(ON) RON RON On Leakage Current of Port 1A and 2A Switch On Resistance(4) See Figure 9 On Resistance Matching Between Channels(5) RFLAT(ON) On Resistance Flatness(6) ICC VIN = 0V to VCC TA= 40 to +85C Units Min. Typ. Max. Min. Max. TA = +25C 2.7 to 3.6 2.
PAGE 6
All typical values are at 25°C unless otherwise specified. Symbol Parameter VCC Conditions (V) VIH VIL IIN Input Voltage High Input Voltage Low Control Input Leakage INO(OFF), Off-Leakage Current of INC(OFF) Port nB0 and nB1 IA(ON) RON RON RFLAT(ON) On Leakage Current of Port 1A and 2A Switch On Resistance(7) On Resistance Matching Between Channels(8) See Figure 10 On Resistance Flatness(9) VIN = 0V to VCC TA= 40 to +85C Units Min. Typ. Max. Min. Max. TA = +25C 3.6 to 4.3 1.7 2.
PAGE 7
All typical values are at 25°C unless otherwise specified. Symbol tON tOFF tBBM Q OIRR Xtalk BW THD Parameter Turn-On Time Turn-Off Time Break-BeforeMake Time Charge Injection Off Isolation Crosstalk -3db Bandwidth Total Harmonic Distortion VCC (V) Conditions nB0 or nB1 = 1.5V, RL = 50, CL = 35 pF nB0 or nB1 = 1.5V, RL = 50, CL = 35 pF nB0 or nB1 = 1.5V, RL = 50, CL = 35 pF TA= -40 to Figure +85°C Units Number Min. Typ. Max. Min. Max. 2.7 to 3.6 30.0 38.0 42.0 2.3 to 2.7 29.
PAGE 8
All typical value are at 25°C unless otherwise specified. Symbol Parameter VCC (V) Conditions TA = +25°C TA= -40 to +85°C Units Figure Number Min. Typ. Max. Min. Max. tON tOFF tBBM Q OIRR Xtalk BW THD Turn-On Time Turn-Off Time Break-BeforeMake Time Charge Injection Off Isolation nB0 or nB1 = 1.5V, RL = 50, CL = 35pF nB0 or nB1 = 1.5V, RL = 50, CL = 35pF -3db Bandwidth Total Harmonic Distortion 37.0 46.0 48.0 2.7 to 3.6 37.0 50.0 57.0 2.3 to 2.7 60 1.65 570 3.6 to 4.
PAGE 9
FSA2267/FSA2267A 0.35 Low-Voltage Dual-SPDT Analog Switch Typical Characteristics Figure 9. RON at 2.7V for FSA2267 Figure 10. RON at 2.7V for FSA2267A © 2005 Fairchild Semiconductor Corporation FSA2267 / FSA2267ARev. 1.0.5 www.fairchildsemi.
PAGE 10
CL includes Fixture and Stray Capacitance. Logic input waveforms are inverted for switches with opposite logic sense. Figure 11. Turn-On/Turn-Off Timing CL Includes Fixture and Stray Capacitance Figure 12. Break-Before-Make Timing Figure 13. Off Isolation and Crosstalk © 2005 Fairchild Semiconductor Corporation FSA2267 / FSA2267A Rev. 1.0.5 www.fairchildsemi.com 10 FSA2267/FSA2267A 0.
PAGE 11
FSA2267/FSA2267A 0.35 Low-Voltage Dual-SPDT Analog Switch AC Loading and Waveforms (Continued) Q = (DVOUT)(CL) Figure 14. Charge Injection Figure 15. On/Off Capacitance Measurement Setup Figure 16. Bandwidth Figure 17. Harmonic Distortion © 2005 Fairchild Semiconductor Corporation FSA2267 / FSA2267A Rev. 1.0.5 www.fairchildsemi.
PAGE 12
1.62 B KEEPOUT ZONE, N OR VIAS ALLOWED (0.11) 0.56 1.12 1.60 IDENT IS ER THAN ER LINES 0.10 C 2X TOP VIEW (0.35) 10X (0.25) 10X 0.50 RECOMMENDED LAND PATTERN 0.55 MAX 0.05 C 0.05 C 0.05 0.00 (0.20) C 0.35 0.25 SIDE VIEW (0.15) D 0.65 0.55 AIL A 0.35 0.25 (0.36) 0.35 0.25 DETAIL A 2X SCALE 4 1 0.56 5 10 (0.29) 0.35 9X 0.25 6 9 0.50 0.25 9X 0.15 1.62 0.10 0.05 C A B C ALL FEATURES BOTTOM VIEW NOTES: A. PACKAGE CONFORMS TO JEDEC REGISTRATION MO-255, VARIATION UABD B.
PAGE 13
FSA2267/FSA2267A 0.35 Low-Voltage Dual-SPDT Analog Switch Physical Dimensions Figure 19. Pb-Free, 10-Lead, Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 14
FSA2267/FSA2267A 0.35 Low-Voltage Dual-SPDT Analog Switch © 2005 Fairchild Semiconductor Corporation FSA2267 / FSA2267A Rev. 1.0.5 www.fairchildsemi.