Datasheet

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FPF2200-FPF2202 Rev. B
FPF2200-FPF2202 Integrated Load Switch with 500mA High Precision Current Limit
Application Information
Input Capacitor
To limit the voltage drop on the input supply caused by transient
in-rush currents when the switch is turned on into a discharged
load capacitor or a short-circuit, a capacitor is recommended to
be placed between V
IN
and GND. A 1uF ceramic capacitor, C
IN
,
placed close to the pins is usually sufficient. Higher values of
C
IN
can be used to further reduce the voltage drop.
Output Capacitor
A 0.1uF capacitor C
OUT
, should be placed between V
OUT
and
GND. This capacitor will prevent parasitic board inductances
from forcing V
OUT
below GND when the switch turns-off. For the
FPF2200 and FPF2201, the total output capacitance needs to
be kept below a maximum value, C
OUT
(max), to prevent the
part from registering an over-current condition and turning-off
the switch. The maximum output capacitance can be
determined from the following formula:
Power Dissipation
During normal on-state operation, the power dissipated in the
device will depend upon the level at which the current limit is
set. The maximum allowed setting for the current limit is 500mA
and will result in a power dissipation of:
If the part goes into current limit, the maximum power
dissipation will occur when the output is shorted to ground. For
the FPF2200, the power dissipation will scale by the Auto-
Restart Time, t
RSTRT
, and the Over Current Blanking Time,
t
BLANK
, so that the maximum power dissipated is:
Note this is below the maximum package power dissipation, and
the thermal shutdown feature will act as additional safety to
protect the part from damage due to excessive heating. The
junction temperature is only able to increase to the thermal
shutdown threshold. Once this temperature has been reached,
toggling ON will not turn-on the switch until the junction
temperature drops. For the FPF2202, a short on the output will
cause the part to operate in a constant current state dissipating
a worst case power of:
This large amount of power will activate the thermal shutdown
and the part will cycle in and out of thermal shutdown so long as
the ON pin is active and the short is present.
PCB Layout Recommendations
For best performance, all traces should be as short as possible.
To be more effective, the input and output capacitors should be
placed close to the device to minimize the effects that parasitic
trace inductances may have on normal and short-circuit
operation. Using wide traces for V
IN
, V
OUT
and GND will help
minimize parasitic electrical effects along with minimizing the
case to ambient thermal impedance.
Improving Thermal Performance
An improper layout could result in higher junction temperature
and triggering the thermal shutdown protection feature. This
concern applies when the switch is set at higher current limit
value and an over-current condition occurs. In this case, the
power dissipation of the switch, from the formula below, could
exceed the maximum absolute power dissipation of 1.2W.
PD = (V
IN
- V
OUT
) x I
LIM (Max)
The following techniques have been identified to improve the
thermal performance of this family of devices. These
techniques are listed in order of the significance of their impact.
1. Thermal performance of the load switch can be improved by
connecting pin7 of the DAP (Die Attach Pad) to the GND plane
of the PCB.
2. Embedding two exposed through-hole vias into the DAP
(pin7) provides a path for heat to transfer to the back GND
plane of the PCB. A drill size of Round, 14 mils (0.35mm) with
1-ounce copper plating is recommended to result in appropriate
solder reflow. A smaller size hole prevents the solder from
penetrating into the via, resulting in device lift-up. Similarly, a
larger via-hole consumes excessive solder, and may result in
voiding of the DAP.
Figure 21: Two through hole open vias embedded in DAP
3. The V
IN
, V
OUT
and GND pins will dissipate most of the heat
generated during a high load current condition. The layout
suggested in Figure 23 provides each pin with adequate copper
so that heat may be transferred as efficiently as possible out of
the device. The low-power FLAGB and ON pin traces may be
laid-out diagonally from the device to maximize the area
available to the ground pad. Placing the input and output
capacitors as close to the device as possible also contributes to
heat dissipation, particularly during high load currents.
C
OUT (Max)
=
I
LIM (Max)
X t
BLANK (Min)
V
IN
P = (I
LIM
)
2
* R
ON
= (0.5)
2
* 0.16 = 40mW
P
(Max)
=
t
BLANK
t
BLANK
+ t
RSTRT
* V
IN (Max)
* I
LIM (Max)
30
30 + 450
* 5.5 * 0.5 = 0.17W
=
P
(Max)
= V
IN (MAX)
* I
LIM (MAX)
= 5.5 * 0.557 = 3.064W