Datasheet

FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FMS6502 Rev. 1.0.0 7
I
2
C Interface
Figure 4. Bit Transfer
O
peration
T
he I
2
C-compatible interface conforms to the I
2
C specifi-
c
ation for Standard Mode. Individual addresses may be
w
ritten, but there is no read capability. The interface con-
s
ists of two lines: a serial data line (SDA) and a serial
c
lock line (SCL). Both lines must be connected to a posi-
t
ive supply through an external resistor. Data transfer
may be initiated only when the bus is not busy.
Bit Transfer
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during the
HIGH period of the clock pulse. Changes in the data line
during this time are interpreted as control signals.
Data line
stable;
data valid
SCL
SDA
Change
of data
allowed
Start and Stop conditions
Both data and clock lines remain HIGH when the bus is
not busy. A HIGH-to-LOW transition of the data line,
w
hile the clock is HIGH, is defined as start condition (S).
A LOW-to-HIGH transition of the data line, while the
clock is HIGH, is defined as stop condition (P).
Figure 5. START and STOP conditions
SP
START condition
STOP condition
SCL
SDA