Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsInterface ICsInterface IC - analogue switches TSSOP 24

Rev. 1.0.0

January 2007

FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry

FMS6502

8-Input, 6-Output Video Switch Matrix with Output Drivers,

Input Clamp, and Bias Circuitry

Features

■ 8 x 6 Crosspoint Switch Matrix

■ Supports SD, PS, and HD 1080i / 1080p Video

■ Input Clamp and Bias Circuitry

■ Doubly Terminated 75Ω Cable Drivers

■ Programmable 0dB or 6dB Gain

■ AC- or DC-Coupled Inputs

■ AC- or DC-Coupled Outputs

■ One-to-One or One-to-Many Input-to-Output

Switching

■ I

-Compatible Digital Interface, Standard Mode

■ 3.3V or 5V Single Supply Operation

■ Pb-Free TSSOP-24 Package

Applications

■ Cable and Satellite Set-Top Boxes

■ TV and HDTV Sets

■ A / V Switchers

■ Personal Video Recorders (PVR)

■ Security and Surveillance

■ Video Distribution

■ Automotive (In-Cabin Entertainment)

Description

The FMS6502 provides eight inputs that can be routed to

any of six outputs. Each input can be routed to one or

more outputs, but only one input may be routed to any

output.

Each input supports an integrated clamp option to set the

output sync tip level of video with sync to ~300mV. Alter-

natively, the input may be internally biased to center out-

put signals without sync (Chroma, Pb, Pr) at ~1.25V.

All outputs are designed to drive a 150Ω DC-coupled

load. Each output can be programmed to provide either

0dB or 6dB of signal gain.

Input-to-output routing and input bias mode functions are

controlled via an I

C-compatible digital interface.

Block Diagram

Figure 1. Block Diagram

Ordering Information

C / B

IN1

OUT1 OUT2 OUT6

C / B

IN2

C / B

IN8

SDA

SCL

VCC (2)

GND (4)

ADDR0

ADDR1

Part Number Pb-Free

Operating

Temperature Range Package Packing Method

FMS6502MTC24 Yes -40°C to 85°C

24-Lead Thin Shrink Small

Ouline Package

Rail

FMS6502MTC24X Yes -40°C to 85°C

24-Lead Thin Shrink Small

Ouline Package

Reel

Summary of content (13 pages)

PAGE 1
FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry Features Description ■ 8 x 6 Crosspoint Switch Matrix The FMS6502 provides eight inputs that can be routed to any of six outputs. Each input can be routed to one or more outputs, but only one input may be routed to any output.
PAGE 2
IN1 GND 1 Pin Description 24 2 GND 23 OUT1 22 OUT2 21 OUT3 FAIRCHILD IN2 3 FMS6502 VDD 4 24L TSSOP IN3 5 20 VDD GND 6 19 OUT4 IN4 7 18 OUT5 ADDR1 8 17 OUT6 IN5 9 16 GND 10 15 IN8 ADDR0 IN6 11 14 SDA SCL 12 13 IN7 Figure 2. Pin Configuration © 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.
PAGE 3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Parameter Min. Max. Unit DC Supply Voltage -0.3 6 V Analog and Digital I/O -0.3 Vcc + 0.
PAGE 4
The I2C-compatibe interface is used to program output enables, input-to-output routing, and input bias configuration. The I2C address of the FMS6502 is 0x06 (0000 0110) with the ability to offset based upon the values of the ADDR0 and ADDR1 inputs.
PAGE 5
TA = 25°C, Vcc = 5V, Vin = 1Vpp, input bias mode, one-to-one routing, 6dB gain, all inputs AC-coupled with 0.1μF, unused inputs AC-terminated through 75Ω to GND, all outputs AC-coupled with 220μF into 150Ω, referenced to 400kHz unless otherwise noted. Symbol ICC VOUT Parameter PSRR Typ. Max. Unit 55 75 mA 2.8 (1) Vpp Clamp Mode, All Gain Settings 0.10 0.15 0.20 V (1) Clamp Mode, 0dB Gain Setting 0.10 0.15 0.20 V DC Output Level(1) Clamp Mode, 6dB Gain Setting 0.20 0.30 0.
PAGE 6
TA = 25°C, Vcc = 5V unless otherwise noted. Symbol Max. Unit Vil Digital Input Low1 Parameter SDA,SCL,ADDR Conditions Min. 0 Typ. 1.5 V Vih 1 Digital Input High SDA,SCL,ADDR 3.0 Vcc V fSCL Clock Frequency SCL 100 kHz tr Input Rise Time 1.5V to 3V 1000 ns tf Input Fall Time 1.5V to 3V 300 ns tlow Clock Low Period 4.7 µs thigh Clock High Period 4.
PAGE 7
Operation The I2C-compatible interface conforms to the I2C specification for Standard Mode. Individual addresses may be written, but there is no read capability. The interface consists of two lines: a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply through an external resistor. Data transfer may be initiated only when the bus is not busy. Bit Transfer One data bit is transferred during each clock pulse.
PAGE 8
The number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter while the master generates an extra acknowledge-related clock pulse. The slave receiver addressed must generate an acknowledge after the reception of each byte.
PAGE 9
Input Clamp / Bias Circuitry Output Configuration The FMS6502 can accommodate AC- or DC-coupled inputs. Internal clamping and bias circuitry are provided to support AC-coupled inputs. These are selectable through the CLMP bits via the I2C-compatible interface. For DC-coupled inputs, the device should be programmed to use the 'bias' input configuration. In this configuration, the input is internally biased to 625mV through a 100kΩ resistor.
PAGE 10
Crosstalk is an important consideration when using the FMS6502. Input and output crosstalk represent the two major coupling modes that may be present in a typical application. Input crosstalk is crosstalk in the input pins and switches when the interfering signal drives an open switch. It is dominated by inductive coupling in the package lead frame between adjacent leads. It decreases rapidly as the interfering signal moves further away from the pin adjacent to the input signal selected.
PAGE 11
General layout and supply bypassing play a major role in high-frequency performance and thermal characteristics. Fairchild offers a demonstration board to guide layout and aid device evaluation. The demo board is a fourlayer board with full power and ground planes. Following this layout configuration provides optimum performance and thermal characteristics for the device. For the best results, follow the steps and recommended routing rules listed below.
PAGE 12
FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 15. 24-Lead Thin Shrink Small Outline Package © 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.0 www.fairchildsemi.
PAGE 13
FMS6502 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry 13 www.fairchildsemi.com © 2006 Fairchild Semiconductor Corporation FMS6502 Rev. 1.0.