Datasheet

FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
© 2004 Fairchild Semiconductor Corporation www.fairchildsemi.com
FMS6501 Rev. 1.0.4 3
Pin Configuration
Figure 2. Pin Configuration
IN1
IN3
OUT2
VCCO
OUT7
20
19
18
1
2
3
4
5
6
7
SCL
OUT6
OUT5
OUT3
17
16
15
8
9
10
OUT1
11
12
13
21
22
23
24
25
26
14
27
28
IN2
OUT4
GNDO
OUT8
OUT9
SDA
ADDR
IN7
IN8
IN9
IN5
IN4
VCC
IN6
IN12
IN11
IN10
GND
FAIRCHILD
FMS6501
28L SSOP
Pin Assignments
Pin# Name Type Description
1 IN1 Input Input, channel 1
2 IN2 Input Input, channel 2
3 IN3 Input Input, channel 3
4 IN4 Input Input, channel 4
5 IN5 Input Input, channel 5
6 IN6 Input Input, channel 6
7 VCC Input Positive power supply
8 GND Input Must be tied to ground
9 IN7 Input Input, channel 7
10 IN8 Input Input, channel 8
11 IN9 Input Input, channel 9
12 IN10 Input Input, channel 10
13 IN11 Input Input, channel 11
14 IN12 Input Input, channel 12
15 ADDR Input
Selects I
2
C address. “0” = 0x06
(0000 0110), ‘1” = 0x86 (1000 0110)
16 SCL Input Serial clock for I
2
C port
17 SDA Input Serial data for I
2
C port
18 OUT9 Output Output, channel 9
19 OUT8 Output Output, channel 8
20 OUT7 Output Output, channel 7
21 GNDO Input Must be tied to ground
22 VCCO Input Positive power supply for output drivers
23 OUT6 Output Output, channel 6
24 OUT5 Output Output, channel 5
25 OUT4 Output Output, channel 4
26 OUT3 Output Output, channel 3
27 OUT2 Output Output, channel 2
28 OUT1 Output Output, channel 1