Datasheet

© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
FMS6403 • Rev. 1.0.4 3
FMS6403 — Triple Video Drivers with Selectable HD/PS/SD Bypass Filters for RGB and YPbPr Signals
Pin Configuration
Figure 3. Pin Configuration
Pin Definitions
Pin # Name Type Description
1 EXT_SYNC Input Selects the external SYNC_IN signal when set to logic 1; do not float.
2 RGB_SEL
Input Selects RGB clamp levels when set to logic 1. YPbPr clamps levels when set to
logic 0; do not float.
3 Y1/G1 Input Y or G input 1 - may be connected to a signal that includes sync.
4 Y2/G2 Input Y or G input 2 - may be connected to a signal that includes sync.
5 Pb1/B1 Input Pb or B input 1.
6 Pb2/B2 Input Pb or B input 2.
7 Pr1/R1 Input Pr or R input 1.
8 Pr2/R2 Input Pr or R input 2.
9 F
SEL0
Input Selects filter corner frequency or bypass, see Table 2. Do not float.
10 F
SEL1
Input Selects filter corner frequency or bypass, see Table 2. Do not float.
11 GND Input Must be tied to ground, do not float.
12 GND Input Must be tired to ground, do not float.
13 0dB_SEL
Input Selects output gain of 0dB when set to logic 1; 6dB when set to logic 0. Do not
float.
14 Pr/R
OUT
Output Pr or R output.
15 Pb/B
OUT
Output Pb or B output.
16 Y/G
OUT
Output Y or G output.
17 In2_SEL
Input Selects MUX input 2 when set to logic 1; MUX input 1 when set to logic 0. Do not
float.
18 SYNC_IN
Input External sync inputs signal, square wave crossing V
IL
and V
IN
input thresholds. Do
not float.
19 V
CC
Input +5V supply. Do not float.
20 V
CC
Input +5V supply. Do not float.