Datasheet

© 2006 Fairchild Semiconductor www.fairchildsemi.com
FMS6346 • Rev. 1.0.5 7
FMS6346 — Six Channel, 6th-Order SD/HD Video FIlter Driver
The same method can be used for biased signals with the
addi tion of a pull-up resistor to make sure the clamp never
operates. The internal pull-down resistance is 800kΩ
±20%, so the exter nal resistance should be 7.5MΩ to set
the DC level to 500mV. If a pull-up resistance less than
7.5MΩ is desired, an external pull-down can be added
such that the DC input level is set to 500mV.
Figure 16. Biased SCART with DC-Coupled Outputs
The same circuits can be used with AC-coupled outputs if
desired, as shown in Figure 17.
Figure 17 DC-Coupled Inputs, AC-Coupled Outputs
Figure 18. AC-Coupled Inputs, AC-Coupled Outputs
Figure 19. Biased SCART with AC-Coupled Outputs
NOTE: The video tilt or line time distortion is dominated by
the AC-coupling capacitor. The value may need to be in-
creased beyond 220F to obtain satisfactory operation in
some applications.
Power Dissipation
The FMS6346 output drive confi guration must be consid-
ered when calculating overall power dissipation. Care
must be taken not to exceed the maximum die junction
temperature. The fol lowing example can be used to calcu-
late the FMS6346’s power dissipation and internal tem-
perature rise:
T
J
= T
A
+ P
d
• θ
JA
where P
d
= P
CH1
+ P
CH2
+ P
CHx
and P
CHx
= V
s
• I
CH
- (V
O
2
/R
L
)
where
V
O
= 2V
in
+ 0.280V
I
CH
= (I
CC
/ 6) + (V
O
/R
L
)
V
IN
= RMS value of input signal
I
CC
= 60mA
V
s
= 5V
R
L
= channel load resistance
Board layout can affect thermal characteristics. Refer to
the Layout Considerations section for more information.
Layout Considerations
General layout and supply bypassing play major roles in
high-frequency performance and thermal characteristics.
Fairchild offers a demonstration board, FMS6346DEMO,
to guide layout and aid device testing and characteriza-
tion. The FMS6346DEMO is a four-layer board with a full
power and ground plane. Following this layout confi gura-
tion pro vides the optimum performance and thermal char-
acteristics. For best results, follow the steps below as a
basis for high-fre quency layout:
• Include 10F and 0.1F ceramic bypass capacitors
• Place the 10F capacitor within 0.75 inches of the
power pin
• Place the 0.1F capacitor within 0.1 inches of the
power pin
• For multi-layer boards, use a large ground plane to
help dissi pate heat
• For two-layer boards, use a ground plane that extends
beyond the device by at least 0.5 inches
• Minimize all trace lengths to reduce series inductances
Output Considerations
The FMS6346 outputs are DC offset from the input by
150mV. Therefore, V
OUT
= 2•V
IN
DC+150mV. This offset is
required to obtain optimal performance from the output
driver and is held at the minimum value to decrease the
standing DC current into the load. Since the FMS6346
has a 2x (6dB) gain, the output is typically connected via a
75-series back-matching resistor, followed by the 75
video cable. Due to the inherent divide by two of this confi -
guration, the blanking level at the load of the video signal
is always less than 1V. When AC-coupling the output,
ensure that the coupling capacitor of choice passes the
lowest frequency content in the video signal and that line
time distortion (video tilt) is kept as low as possible.
LCVF
Bias
Input
0.1μF
External video
source must
be AC coupled
500mV +/-350mV
75Ω
7.5MΩ
75Ω
DVD or
STB
SoC
DAC
Output
LCVF
Clamp
Inactive
0V - 1.4V
220µF
75Ω
DVD or
STB
SoC
DAC
Output
LCVF
Clamp
Active
0.1μF
0V - 1.4V
75Ω
220μF
LCVF
Clamp
Active
0.1μF
External video
source must
be AC coupled.
500mV +/-350mV
220μF
75Ω
7.5MΩ
75Ω