Datasheet

FDMC8030 Dual N-Channel Power Trench
®
MOSFET
www.fairchildsemi.com
2
©2011 Fairchild Semiconductor Corporation
FDMC8030 Rev.C1
Electrical Characteristics T
J
= 25 °C unless otherwise noted
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
Drain-Source Diode Characteristics
Symbol Parameter Test Conditions Min Typ Max Units
BV
DSS
Drain to Source Breakdown Voltage I
D
= 250 μA, V
GS
= 0 V 40 V
ΔBV
DSS
ΔT
J
Breakdown Voltage Temperature
Coefficient
I
D
= 250 μA, referenced to 25 °C 19 mV/°C
I
DSS
Zero Gate Voltage Drain Current V
DS
= 32 V, V
GS
= 0 V 1 μA
I
GSS
Gate to Source Leakage Current, Forward V
GS
= 12 V, V
DS
= 0 V 100 nA
V
GS(th)
Gate to Source Threshold Voltage V
GS
= V
DS
, I
D
= 250 μA 1.0 1.5 2.8 V
ΔV
GS(th)
ΔT
J
Gate to Source Threshold Voltage
Temperature Coefficient
I
D
= 250 μA, referenced to 25 °C -5 mV/°C
r
DS(on)
Static Drain to Source On Resistance
V
GS
= 10 V, I
D
= 12 A 8 10
mΩ
V
GS
= 4.5 V, I
D
= 10 A 10 14
V
GS
= 3.2 V, I
D
= 4 A 19 28
V
GS
= 10 V, I
D
= 12 A
T
J
= 125 °C
13 16
g
FS
Forward Transconductance V
DD
= 5 V, I
D
= 12 A 57 S
C
iss
Input Capacitance
V
DS
= 20 V, V
GS
= 0 V
f = 1MHz
1462 1975 pF
C
oss
Output Capacitance 321 430 pF
C
rss
Reverse Transfer Capacitance 20 30 pF
R
g
Gate Resistance 0.9 2.5 Ω
t
d(on)
Turn-On Delay Time
V
DD
= 20 V, I
D
= 12 A
V
GS
= 10 V, R
GEN
= 6 Ω
713ns
t
r
Rise Time 310ns
t
d(off)
Turn-Off Delay Time 19 33 ns
t
f
Fall Time 310ns
Q
g(TOT)
Total Gate Charge V
GS
= 0 V to 10 V
V
DD
= 20 V
I
D
= 12 A
21 30 nC
Total Gate Charge V
GS
= 0 V to 5 V 12 17 nC
Q
gs
Gate to Source Charge 2.8 nC
Q
gd
Gate to Drain “Miller” Charge 2.5 nC
V
SD
Source to Drain Diode Forward Voltage V
GS
= 0 V, I
S
= 12 A (Note 2) 0.83 1.2 V
t
rr
Reverse Recovery Time
I
F
= 12 A, di/dt = 100 A/μs
25 40 ns
Q
rr
Reverse Recovery Charge 9 18 nC
NOTES:
1. R
θJA
is determined with the device mounted on a 1 in
2
pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
θJC
is guaranteed by design while R
θCA
is determined by
the user's board design.
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %.
3. E
AS
of 21 mJ is based on starting T
J
= 25
o
C, L = 0.3 mH, I
AS
= 12 A, V
DD
= 36 V, V
GS
= 10 V. 100% tested at L = 3 mH, I
AS
= 5 A.
4. As an N-ch device, the negative V
gs
rating is for low duty cycle pulse occurence only. No continuous rating is implied.
a. 65 °C/W when mounted on
a 1 i n
2
pad of 2 oz copper
b.155 °C/W when mounted on
a minimum pad of 2 oz copper