Datasheet

©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC74 — Dual D-Type Flip-Flop with Preset and Clear
AC Electrical Characteristics
Note:
3. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained from the equation:
I
CC
(opr.) = C
PD
• V
CC
• f
IN
+ I
CC
/ 2 (per F/F).
AC Operating Requirements
Note:
4. V
CC
is 3.3 ± 0.3V or 5.0 ± 0.5V
Symbol Parameter V
CC
(V) Conditions
T
A
= 25°C
T
A
= –40°C
to +85°C
UnitsMin. Typ. Max. Min. Max.
f
MAX
Maximum Clock
Frequency
3.3 ± 0.3 C
L
= 15pF 80 125 70 MHz
C
L
= 50pF 50 75 45
5.0 ± 0.5 C
L
= 15pF 130 170 110
C
L
= 50pF 90 115 75
t
PLH
, t
PHL
Propagation Delay
Time (CK-Q, Q
)
3.3 ± 0.3 C
L
= 15pF 6.7 11.9 1.0 14.0 ns
C
L
= 50pF 9.2 15.4 1.0 17.5
5.0 ± 0.5 C
L
= 15pF 4.6 7.3 1.0 8.5
C
L
= 50pF 6.1 9.3 1.0 10.5
t
PLH
, t
PHL
Propagation Delay
Time (CLR, PR -Q, Q)
3.3 ± 0.3 C
L
= 15pF 7.6 12.3 1.0 14.5 ns
C
L
= 50pF 10.1 15.8 1.0 18.0
5.0 ± 0.5 C
L
= 15pF 4.8 7.7 1.0 9.0
C
L
= 50pF 6.3 9.7 1.0 11.0
C
IN
Input Capacitance V
CC
= Open 4 10 10 pF
C
PD
Power Dissipation
Capacitance
(3)
25 pF
Symbol Parameter V
CC
(V)
(4)
T
A
= 25°C
T
A
= –40°C
to +85°C
UnitsTyp.
Guaranteed
Minimum
t
W
(L), t
W
(H) Minimum Pulse Width (CK) 3.3 6.0 7.0 ns
5.0 5.0 5.0
t
W
(L) Minimum Pulse Width (CLR, PR) 3.3 6.0 7.0 ns
5.0 5.0 5.0
t
S
Minimum Setup Time 3.3 6.0 7.0 ns
5.0 5.0 5.0
t
H
Minimum Hold Time 3.3 0.5 0.5 ns
5.0 0.5 0.5
t
REC
Minimum Recovery Time (CLR, PR) 3.3 5.0 5.0 ns
5.0 3.0 3.0
74VHC74 Rev. 1.3.1 5