Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsLogic ICsLogic IC - Latch Transparent D latch Three-state TSSOP 20

74VHC573 Octal D-Type Latch with 3-STATE Outputs

May 2007

74VHC573 Rev. 1.3

74VHC573

Octal D-Type Latch with 3-STATE Outputs

Features

■

High Speed: t

5.0ns (Typ.) at V

■

High Noise Immunity: V

NIH

NIL

28% V

(Min.)

■

Power Down Protection is provided on all inputs

■

Low Noise: V

OLP

0.6V (Typ.)

■

Low Power Dissipation: I

4µA (Max.) @ T

25°C

■

Pin and function compatible with 74HC573

General Description

The VHC573 is an advanced high speed CMOS octal

latch with 3-STATE output fabricated with silicon gate

CMOS technology. It achieves the high speed operation

similar to equivalent Bipolar Schottky TTL while main-

taining the CMOS low power dissipation. This 8-bit

D-type latch is controlled by a latch enable input (LE)

and an Output Enable input (OE

). When the OE input is

HIGH, the eight outputs are in a high impedance state.

An input protection circuit ensures that 0V to 7V can be

applied to the input pins without regard to the supply

voltage. This device can be used to interface 5V to 3V

systems and two supply systems such as battery back

up. This circuit prevents device destruction due to mis-

matched supply and input voltages.

Ordering Information

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the

ordering number. Pb-Free package per JEDEC J-STD-020B.

Connection Diagram

Pin Description

Order Number Package

Number

Package Description

74VHC573M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74VHC573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Pin Names Description

–D

Data Inputs

LE Latch Enable Input

3-STATE Output Enable Input

–O

3-STATE Outputs

Summary of content (9 pages)

PAGE 1
74VHC573 Octal D-Type Latch with 3-STATE Outputs tm Features General Description ■ High Speed: tPD = 5.0ns (Typ.) at VCC = 5V ■ High Noise Immunity: VNIH = VNIL = 28% VCC (Min.) The VHC573 is an advanced high speed CMOS octal latch with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.
PAGE 2
Functional Description IEEE/IEC The VHC573 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs, a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input.
PAGE 3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Rating VCC Supply Voltage –0.5V to +7.0V VIN DC Input Voltage –0.5V to +7.
PAGE 4
TA = 25°C Symbol Parameter VIH HIGH Level Input Voltage VIL LOW Level Input Voltage VOH HIGH Level Output Voltage VCC (V) Conditions Min. 2.0 1.50 3.0–5.5 0.7 x VCC 2.0 3.0 2.0 1.9 2.9 3.0 2.9 4.4 4.5 4.4 IOH = –4mA 2.58 2.48 IOH = –8mA 3.94 3.80 VIN = VIH IOL = 50µA or VIL 3.0 4.5 IIN Input Leakage Current ICC Quiescent Supply Current V 0.0 0.1 0.1 0.0 0.1 0.1 0.0 IOL = 4mA IOL = 8mA V 0.3 x VCC 1.9 4.5 3.0 V 0.50 0.
PAGE 5
TA = –40°C to +85°C TA = 25°C Symbol tPLH, tPHL Parameter Propagation Delay Time (LE to On) VCC (V) 3.3 ± 0.3 5.0 ± 0.5 tPLH, tPHL Propagation Delay Time (D–On) 3.3 ± 0.3 5.0 ± 0.5 tPZL, tPZH 3-STATE Output Enable Time 3.3 ± 0.3 RL = 1kΩ 3-STATE Output Disable Time 3.3 ± 0.3 tOSLH, tOSHL Output to Output Skew 3.3 ± 0.3 CIN COUT CPD Typ. Max. Min. Max. Units ns CL = 15pF 7.6 11.9 1.0 14.0 CL = 50pF 10.1 15.4 1.0 17.5 CL = 15pF 5.0 7.7 1.0 9.0 CL = 50pF 6.5 9.7 1.0 11.
PAGE 6
74VHC573 Octal D-Type Latch with 3-STATE Outputs Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B ©1993 Fairchild Semiconductor Corporation 74VHC573 Rev. 1.3 www.fairchildsemi.
PAGE 7
4VHC573 Octal D-Type Latch with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D ©1993 Fairchild Semiconductor Corporation 74VHC573 Rev. 1.3 www.fairchildsemi.
PAGE 8
74VHC573 Octal D-Type Latch with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 ©1993 Fairchild Semiconductor Corporation 74VHC573 Rev. 1.3 www.fairchildsemi.
PAGE 9
® ACEx Across the board. Around the world.