Datasheet

74VHC374 Octal D-Type Flip-Flop with 3-STATE Outputs
©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC374 Rev. 1.3 5
AC Electrical Characteristics
Notes:
3. Parameter guaranteed by design. t
OSLH
= |t
PLH max
– t
PLH min
|; t
OSHL
= |t
PHL max
– t
PHL min
|
4. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained by the equation:
I
CC
(opr.) = C
PD
• V
CC
• f
IN
+ I
CC
/ 8 (per F/F). The total C
PD
when n pcs. of the Octal D Flip-Flop operates
can be calculated by the equation: C
PD
(total) = 20 + 12n.
AC Operating Requirements
Symbol Parameter V
CC
(V) Conditions
T
A
= 25°C
T
A
= –40°C
to +85°C
UnitsMin. Typ. Max. Min. Max.
t
PLH
, t
PHL
Propagation Delay
Time (CP to O
n
)
3.3 ± 0.3 C
L
= 15pF 8.1 12.7 1.0 15.0 ns
C
L
= 50pF 10.6 16.2 1.0 18.5
5.0 ± 0.5 C
L
= 15pF 5.4 8.1 1.0 9.5 ns
C
L
= 50pF 6.9 10.1 1.0 11.5
t
PZL
, t
PZH
3-STATE Output
Enable Time
3.3 ± 0.3 R
L
= 1kΩ C
L
= 15pF 7.1 11.0 1.0 13.0 ns
C
L
= 50pF 9.6 14.5 1.0 16.5
5.0 ± 0.5 C
L
= 15pF 5.1 7.6 1.0 9.0 ns
C
L
= 50pF 6.6 9.6 1.0 11.0
t
PLZ
, t
PHZ
3-STATE Output
Disable Time
3.3 ± 0.3 R
L
= 1kΩ C
L
= 50pF 10.2 14.0 1.0 16.0 ns
5.0 ± 0.5 C
L
= 50pF 6.1 8.8 1.0 10.0
t
OSLH
,
t
OSHL
Output to Output
Skew
3.3 ± 0.3
(3)
C
L
= 50pF 1.5 1.5 ns
5.0 ± 0.5 C
L
= 50pF 1.0 1.0
f
MAX
Maximum Clock
Frequency
3.3 ± 0.3 C
L
= 15pF 80 130 70 MHz
C
L
= 50pF 55 85 50
5.0 ± 0.5 C
L
= 15pF 130 185 110
C
L
= 50pF 85 120 75
C
IN
Input Capacitance V
CC
= Open 4 10 10 pF
C
OUT
Output Capacitance V
CC
= 5.0V 6 pF
C
PD
Power Dissipation
Capacitance
(4)
32 pF
Symbol Parameter V
CC
(V)
T
A
= 25°C T
A
= –40°C to +85°C
UnitsMin. Typ. Max. Min. Max.
t
W
(H), t
W
(L) Minimum Pulse Width
(CP)
3.3 ± 0.3 5.0 5.5 ns
5.0 ± 0.5 5.0 5.0
t
S
Minimum Set-Up Time 3.3 ± 0.3 4.5 4.5 ns
5.0 ± 0.5 3.0 3.0
t
H
Minimum Hold Time 3.3 ± 0.3 2.0 2.0 ns
5.0 ± 0.5 2.0 2.0