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74VHC374 Octal D-Type Flip-Flop with 3-STATE Outputs

April 2007

74VHC374 Rev. 1.3

74VHC374

Octal D-Type Flip-Flop with 3-STATE Outputs

Features

■

High Speed: t

5.4ns (typ) at V

■

High noise immunity: V

NIH

NIL

28% V

(Min.)

■

Power down protection is provided on all inputs

■

Low power dissipation: I

4µA (Max) @ T

25°C

■

Pin and function compatible with 74HC374

General Description

The VHC374 is an advanced high speed CMOS octal

flip-flop with 3-STATE output fabricated with silicon gate

CMOS technology. It achieves the high speed operation

similar to equivalent Bipolar Schottky TTL while main-

taining the CMOS low power dissipation. This 8-bit

D-type flip-flop is controlled by a clock input (CP) and an

output enable input (OE

). When the OE input is HIGH,

the eight outputs are in a HIGH impedance state.

An input protection circuit ensures that 0V to 7V can be

applied to the input pins without regard to the supply

voltage. This device can be used to interface 5V to 3V

systems and two supply systems such as battery back

up. This circuit prevents device destruction due to mis-

matched supply and input voltages.

Ordering Information

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the

ordering number. Pb-Free package per JEDEC J-STD-020B.

Connection Diagram Pin Descriptions

Order

Number

Package

Number Package Description

74VHC374M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74VHC374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC374MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Pin Names Description

–D

Data Inputs

CP Clock Pulse Input

3-STATE Output Enable Input

–O

3-STATE Outputs

Summary of content (9 pages)

PAGE 1
74VHC374 Octal D-Type Flip-Flop with 3-STATE Outputs tm Features General Description ■ High Speed: tPD = 5.4ns (typ) at VCC = 5V ■ High noise immunity: VNIH = VNIL = 28% VCC (Min.) The VHC374 is an advanced high speed CMOS octal flip-flop with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.
PAGE 2
Functional Description IEEE/IEC The VHC374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs.
PAGE 3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Rating VCC Supply Voltage –0.5V to +7.0V VIN DC Input Voltage –0.5V to +7.
PAGE 4
TA = 25°C Symbol Parameter VIH HIGH Level Input Voltage VIL LOW Level Input Voltage VOH HIGH Level Output Voltage VCC (V) Conditions Min. 2.0 1.50 3.0–5.5 0.7 x VCC 3.0 LOW Level Output Voltage Min. 0.50 2.0 1.9 2.9 3.0 2.9 4.4 4.5 4.4 V IOH = –4mA 2.58 2.48 IOH = –8mA 3.94 3.80 VIN = VIH IOL = 50µA or VIL 4.5 3.0 4.5 0.0 0.1 0.1 0.0 0.1 0.1 0.0 IOL = 4mA IOL = 8mA V 0.3 x VCC 1.9 4.5 2.0 V 0.3 x VCC VIN = VIH IOH = –50µA or VIL Units 0.7 x VCC 3.0 3.
PAGE 5
TA = –40°C to +85°C TA = 25°C Symbol Parameter tPLH, tPHL Propagation Delay Time (CP to On) VCC (V) Conditions 3.3 ± 0.3 5.0 ± 0.5 tPZL, tPZH 3-STATE Output Enable Time 3.3 ± 0.3 RL = 1kΩ Typ. Max. Min. Max. Units CL = 15pF 8.1 12.7 1.0 15.0 CL = 50pF 10.6 16.2 1.0 18.5 CL = 15pF 5.4 8.1 1.0 9.5 CL = 50pF 6.9 10.1 1.0 11.5 CL = 15pF 7.1 11.0 1.0 13.0 CL = 50pF 9.6 14.5 1.0 16.5 CL = 15pF 5.1 7.6 1.0 9.0 CL = 50pF 6.6 9.6 1.0 11.0 3.3 ± 0.
PAGE 6
74VHC374 Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 2. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B ©1992 Fairchild Semiconductor Corporation 74VHC374 Rev. 1.3 www.fairchildsemi.
PAGE 7
4VHC374 Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 3. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D ©1992 Fairchild Semiconductor Corporation 74VHC374 Rev. 1.3 www.fairchildsemi.
PAGE 8
74VHC374 Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 4. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 ©1992 Fairchild Semiconductor Corporation 74VHC374 Rev. 1.3 www.fairchildsemi.
PAGE 9
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