Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsLogic ICsLogic IC - Gate and inverter XOR gate 74VCX TSSOP 14

July 1999

Revised December 2013

74VCX86 Low Voltage Quad 2-Input Exclusive-OR Gate with 3.6V Tolerant Inputs and Outputs

74VCX86

Low Voltage Quad 2-Input Exclusive-OR Gate with

3.6V Tolerant Inputs and Outputs

General Description

The VCX86 contains four 2-input exclusive OR gates. This

product is designed for low voltage (1.2V to 3.6V) V

applications with I/O compatibility up to 3.6V

The 74VCX86 is fabricated with an advanced CMOS tech-

nology to achieve high-speed operation while maintaining

low CMOS power dissipation.

Features

■

1.2V to 3.6V V

supply operation

■

3.6V tolerant inputs and outputs

■

3.0 ns max for 3.0V to 3.6V V

■

Power-off high impedance inputs and outputs

■

Static Drive (I

)

24 mA @ 3.0V V

■

Latchup performance exceeds JEDEC 78 conditions

■

ESD performance:

Human body model 2000V

Machine model

250V

■

Leadless Pb-Free DQFN package

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Note 1: DQFN package available in Tape and Reel only.

Order Number Package Number Package Description

74VCX86M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74VCX86BQX

(Note 1)

MLP014A Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC

MO-241, 2.5 x 3.0mm

74VCX86MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

■

Uses proprietary noise/EMI reduction circuitr

Summary of content (10 pages)

PAGE 1
74VCX86 Low Voltage Quad 2-Input Exclusive-OR Gate with 3.6V Tolerant Inputs and Outputs General Description Features The VCX86 contains four 2-input exclusive OR gates. This product is designed for low voltage (1.2V to 3.6V) VCC applications with I/O compatibility up to 3.6V ■ 1.2V to 3.6V VCC supply operation The 74VCX86 is fabricated with an advanced CMOS technology to achieve high-speed operation while maintaining low CMOS power dissipation. ■ 3.6V tolerant inputs and outputs ■ tPD 3.
PAGE 2
74VCX86 Logic Symbol Connection Diagrams IEEE/IEC Pin Assignments for SOIC and TSSOP Pin Descriptions Pin Names Pad Assignments for DQFN Description An, Bn Inputs On Outputs DAP No Connect Note: DAP (Die Attach Pad) (Top View) www.fairchildsemi.
PAGE 3
Recommended Operating Conditions (Note 4) 0.5V to 4.6V 0.5V to 4.6V Supply Voltage (VCC) DC Input Voltage (VI) Power Supply Output Voltage (VO) Operating HIGH or LOW State (Note 3) VCC 74VCX86 Absolute Maximum Ratings(Note 2) 0V DC Input Diode Current (IIK) VI 0V 0.5V to VCC 0.5V 0.5V to 4.6V 50 mA Output Voltage (VO) HIGH or LOW State DC Output Diode Current (IOK) VO ! VCC 50 mA 50 mA VCC 3.0V to 3.6V VCC 2.3V to 2.7V VCC 1.65V to 2.3V r50 mA VCC 1.4V to 1.6V VCC 1.
PAGE 4
74VCX86 DC Electrical Characteristics Symbol (Continued) Parameter VCC Conditions Min Max Units (V) VOL LOW Level Output Voltage IOL 100 PA 2.7 - 3.6 0.2 IOL 12 mA 2.7 0.4 IOL 18 mA 3.0 0.4 IOL 24 mA 3.0 0.55 IOL 100 PA 2.3 - 2.7 0.2 IOL 12 mA 2.3 0.4 IOL 18 mA 2.3 0.6 IOL 100 PA 1.65 - 2.3 0.2 IOL 6 mA 1.65 0.3 IOL 100 PA IOL 2 mA IOL 100 PA II Input Leakage Current 0 d VI d 3.6V IOFF Power-OFF Leakage Current 0 d (VI, VO) d 3.
PAGE 5
Symbol VOLP VOLV VOHV Parameter VCC Conditions Quiet Output Dynamic Peak VOL CL Quiet Output Dynamic Valley VOL CL Quiet Output Dynamic Valley VOH CL 30 pF, VIH VCC, VIL 30 pF, VIH 0V VCC, VIL 30 pF, VIH 0V VCC, VIL 0V TA 25qC (V) Typical 1.8 0.25 2.5 0.6 3.3 0.8 1.8 0.25 2.5 0.6 3.3 0.8 1.8 1.5 2.5 1.9 3.3 2.2 Units V V V Capacitance Symbol Parameter TA Conditions CIN Input Capacitance VCC COUT Output Capacitance VI 0V or VCC, VCC 1.8, 2.
PAGE 6
74VCX86 AC Loading and Waveforms (VCC 1.5V r 0.1V to 1.2V) TEST SWITCH tPLH, tPHL Open tPZL, tPLZ 1.5 r 0.1V VCC x 2 at VCC tPZH, tPHZ GND FIGURE 3. AC Test Circuit FIGURE 4. Waveform for Inverting and Non-Inverting Functions VCC Symbol www.fairchildsemi.com 1.5V r 0.
PAGE 7
Tape Format for DQFN Package Designator BQX Tape Number Cavity Section Cavities Status Cover Tape Status Leader (Start End) 125 (typ) Empty Sealed Carrier 2500/3000 Filled Sealed Trailer (Hub End) 75 (typ) Empty Sealed TAPE DIMENSIONS inches (millimeters) REEL DIMENSIONS inches (millimeters) Tape Size 12 mm A B C D N W1 W2 13.0 0.059 0.512 0.795 7.008 0.488 0.724 (330) (1.50) (13.00) (20.20) (178) (12.4) (18.4) 7 www.fairchildsemi.
PAGE 8
74VCX86 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A www.fairchildsemi.
PAGE 9
74VCX86 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm Package Number MLP014A 9 www.fairchildsemi.
PAGE 10
74VCX86 Low Voltage Quad 2-Input Exclusive-OR Gate with 3.6V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.