Datasheet

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September 1999

Revised April 2005

74LVX541 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs

74LVX541

Low Voltage Octal Buffer/Line Driver with

3-STATE Outputs

General Description

The LVX541 is an octal non-inverting buffer and line driver

designed to be employed as a memory address driver,

clock driver and bus oriented transmitter or receiver which

provides improved PC board density. The inputs tolerate up

to 7V allowing interface of 5V systems to 3V systems.

Features

■ Input voltage translation from 5V to 3V

■ Ideal for low power/low noise 3.3V applications

■ Guaranteed simultaneous switching noise level and

dynamic threshold performance

Ordering Code:

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Connection Diagram Logic Symbol

IEEE/IEC

Pin Descriptions Truth Table

H HIGH Voltage Level X Immaterial

LOW Voltage Level Z High Impedance

Order Number Package Number Package Description

74LVX541M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74LVX541SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LVX541MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pin Names Descriptions

, OE

3-STATE Output Enable Inputs

- I

Inputs

- O

3-STATE Outputs

Inputs

Outputs

LLHH

HXXZ

XHXZ

LLLL

Summary of content (6 pages)

PAGE 1
Revised April 2005 74LVX541 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs General Description Features The LVX541 is an octal non-inverting buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems. ■ Input voltage translation from 5V to 3V ■ Ideal for low power/low noise 3.
PAGE 2
74LVX541 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) 0.5V to 7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI 20 mA Output Voltage (VO) DC Output Diode Current (IOK) VO 0V to 5.5V Input Voltage (VI) 0.5V to 7V DC Input Voltage (VI) VO 2.0V to 3.6V Supply Voltage (VCC) 0.5V 0V to VCC 40qC to 85qC Operating Temperature (TA) 0.5V VCC 0.5V 20 mA 20 mA 0.5V to VCC 0.
PAGE 3
Symbol VCC Parameter tPLH Propagation Delay tPHL Time (V) TA Min 2.7 3.3 r 0.3 tPZL 3-STATE Output tPZH Enable Time 2.7 25qC TA Max 6.1 11.3 1.0 13.5 CL 15 pF 8.6 14.9 1.0 17.0 CL 50 pF 4.7 7.0 1.0 8.5 CL 15 pF 7.2 10.5 1.0 12.0 CL 50 pF 7.1 13.8 1.0 16.5 CL 15 pF RL 1 k: CL 50 pF RL 1 k: CL 15 pF RL 1 k: CL 50 pF RL 1 k: CL 50 pF RL 1 k: CL 50 pF 17.3 6.8 1.0 10.5 1.0 14.0 ns 20.0 ns 12.5 1.0 16.0 tPLZ 3-STATE Output 2.7 11.
PAGE 4
74LVX541 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B www.fairchildsemi.
PAGE 5
74LVX541 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.
PAGE 6
74LVX541 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.