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74LVX00 — Low Voltage Quad 2-Input NAND Gate
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LVX00 Rev. 1.4.0
February 2008
74LVX00
Low Voltage Quad 2-Input NAND Gate
Features
■
Input voltage level translation from 5V to 3V
■
Ideal for low power/low noise 3.3V applications
■
Guaranteed simultaneous switching noise level and
dynamic threshold performance
General Description
The LVX00 contains four 2-input NAND gates. The
inputs tolerate voltages up to 7V allowing the interface of
5V systems to 3V systems.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Pin Description
Logic Symbol
IEEE/IEC
Order
Number
Package
Number Package Description
74LVX00M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LVX00SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
A
n
, B
n
Inputs
O
n
Outputs

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