Datasheet

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74LCXR2245 — Low Voltage Bidirectional Transceiver with 5V Tolerant Inputs and Outputs and 26

Ω

Series Resistors

on Both A and B Ports

74LCXR2245 Rev. 1.2.0

March 2008

74LCXR2245

Low Voltage Bidirectional Transceiver with 5V Tolerant Inputs

and Outputs and 26

Ω

Series Resistors on Both A and B Ports

Features

■

5V tolerant inputs and outputs

■

2.3V–3.6V V

specifications provided

■

8.0ns t

max. (V

3.3V), 10µA I

max.

■

Power down high impedance inputs and outputs

■

Supports live insertion/withdrawal

(1)

■

±12mA output drive (V

3.0V)

■

Latch-up performance exceeds 500mA

■

Equivalent 26

Ω

series resistor on all outputs

■

ESD performance:

– Human body model

2000V

– Machine model

200V

Note:

1. To ensure the high-impedance state during power up

or down, OE

should be tied to V

through a pull-up

resistor: the minimum value or the resistor is

determined by the current-sourcing capability of the

driver.

General Description

The LCXR2245 contains eight non-inverting bidirectional

buffers with 3-STATE outputs and is intended for bus ori-

ented applications. The device is designed for low volt-

age (2.5V and 3.3V) V

applications with capability of

interfacing to a 5V signal environment. The T/R

input

determines the direction of data flow through the device.

The OE

input disables both the A and B ports by placing

them in a high impedance state. The 26

Ω

series resistor

helps reduce output overshoot and undershoot.

The LCXR2245 is fabricated with an advanced CMOS

technology to achieve high speed operation while main-

taining CMOS low power dissipation.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order Number

Package

Number Package Description

74LCXR2245WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74LCXR2245SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LCXR2245MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

74LCXR2245MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

Implements proprietary noise/EMI reduction circuitry

Summary of content (12 pages)

PAGE 1
74LCXR2245 Low Voltage Bidirectional Transceiver with 5V Tolerant Inputs and Outputs and 26Ω Series Resistors on Both A and B Ports Features General Description ■ 5V tolerant inputs and outputs The LCXR2245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is designed for low voltage (2.5V and 3.3V) VCC applications with capability of interfacing to a 5V signal environment.
PAGE 2
Logic Symbol Truth Table Inputs Pin Description Pin Names Description OE T/R Outputs L L Bus B0 – B7 Data to Bus A0 – A7 L H Bus A0 – A7 Data to Bus B0 – B7 H X HIGH Z State on A0 – A7, B0 – B7(2) OE Output Enable Input H = HIGH Voltage Level T/R Transmit/Receive Input L = LOW Voltage Level A0–A7 Side A Inputs or 3-STATE Outputs X = Immaterial B0–B7 Side B Inputs or 3-STATE Outputs Z = High Impedance Note: 2. Unused bus terminals during HIGH Z State must be held HIGH or LOW.
PAGE 3
Symbol VCC Parameter Rating Supply Voltage –0.5V to +7.0V VI DC Input Voltage –0.5V to +7.0V VO DC Output Voltage Output in 3-STATE –0.5V to +7.0V Output in HIGH or LOW State(3) IIK DC Input Diode Current, VI < GND IOK DC Output Diode Current –0.5V to VCC + 0.5V –50mA VO < GND –50mA VO > VCC +50mA IO DC Output Source/Sink Current ±50mA ICC DC Supply Current per Supply Pin ±100mA IGND DC Ground Current per Ground Pin ±100mA TSTG Storage Temperature –65°C to +150°C Note: 3.
PAGE 4
TA = –40°C to +85°C Symbol VIH VIL VOH VOL Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage VCC (V) Conditions Min 2.3–2.7 1.7 2.7–3.6 2.0 Max V 2.3–2.7 0.7 2.7–3.6 0.8 2.3–3.6 IOH = –100µA IOH = –4mA 1.8 2.7 IOH = –4mA 2.2 3.0 IOH = –6mA 2.4 2.7 IOH = –8mA 2.0 3.0 IOH = –12mA 2.0 V IOL = 100µA 0.2 2.3 IOL = 4mA 0.6 2.7 IOL = 4mA 0.4 3.0 IOL = 6mA 0.55 2.7 IOL = 8mA 0.6 3.0 IOL = 12mA 0.8 2.3–3.
PAGE 5
TA = 25°C Symbol Parameter VCC (V) VOLP Quiet Output Dynamic Peak VOL 3.3 VOLV Quiet Output Dynamic Valley VOL Conditions Typical Unit CL = 50pF, VIH = 3.3V, VIL = 0V 0.5 V 2.5 CL = 30pF, VIH = 2.5V, VIL = 0V 0.4 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V 0.5 2.5 CL = 30pF, VIH = 2.5V, VIL = 0V 0.4 V Capacitance Symbol Parameter Conditions Typical Units Input Capacitance VCC = Open, VI = 0V or VCC 7 pF COUT Output Capacitance VCC = 3.
PAGE 6
Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V VCC x 2 at VCC = 2.5 ± 0.2V tPZH, tPHZ GND Figure 1. AC Test Circuit (CL includes probe and jig capacitance) Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic 3-STATE Output Low Enable and Disable Times for Logic trise and tfall VCC Symbol 3.3V ± 0.3V 2.7V 2.5V ± 0.
PAGE 8
13.00 12.60 A 11.43 20 11 B 9.50 10.65 7.60 10.00 7.40 2.25 1 PIN ONE INDICATOR 0.51 0.35 1.27 0.25 M 10 0.65 1.27 C B A LAND PATTERN RECOMMENDATION 2.65 MAX SEE DETAIL A 0.33 0.20 C 0.75 0.25 X 45° SEATING PLANE NOTES: UNLESS OTHERWISE SPECIFIED (R0.10) GAGE PLANE (R0.10) 0.10 C 0.30 0.10 0.25 8° 0° A) THIS PACKAGE CONFORMS TO JEDEC MS-013, VARIATION AC, ISSUE E B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) CONFORMS TO ASME Y14.
PAGE 9
Figure 4. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 10
Figure 5. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 11
Figure 6. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 12
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