Datasheet

©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
DC Electrical Characteristics
AC Electrical Characteristics
Note:
4. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate
outputs of the same device. The specification applies to any outputs switching in the same direction, either
HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Symbol Parameter V
CC
(V) Conditions
T
A
= –40°C to +85°C
UnitsMin. Max.
V
IH
HIGH Level Input Voltage 2.3–2.7 1.7 V
2.7–3.6 2.0
V
IL
LOW Level Input Voltage 2.3–2.7 0.7 V
2.7–3.6 0.8
V
OH
HIGH Level Output Voltage 2.3–3.6 I
OH
= –100µA V
CC
– 0.2 V
2.3 I
OH
= –8mA 1.8
2.7 I
OH
= –12mA 2.2
3.0 I
OH
= –18mA 2.4
I
OH
= –24mA 2.2
V
OL
LOW Level Output Voltage 2.3–3.6 I
OL
= 100µA 0.2 V
2.3 I
OL
= 8mA 0.6
2.7 I
OL
= 12mA 0.4
3.0 I
OL
= 16mA 0.4
I
OL
= 24mA 0.55
I
I
Input Leakage Current 2.3–3.6 0 ≤ V
I
≤ 5.5V ±5.0 µA
I
OFF
Power-Off Leakage Current 0 V
I
or V
O
= 5.5V 10 µA
I
CC
Quiescent Supply Current 2.3–3.6 V
I
= V
CC
or GND 10 µA
3.6V ≤ V
I
≤ 5.5V ±10
∆I
CC
Increase in I
CC
per Input 2.3–3.6 V
IH
= V
CC
– 0.6V 500 µA
Symbol Parameter
T
A
= –40°C to +85°C, R
L
= 500Ω
Units
V
CC
= 3.3V ± 0.3V,
C
L
= 50pF
V
CC
= 2.7V,
C
L
= 50pF
V
CC
= 2.5V ± 0.2V,
C
L
= 30pF
Min. Max. Min. Max. Min. Max.
f
MAX
Maximum Clock Frequency 150 150 150 MHz
t
PHL
, t
PLH
Propagation Delay,
CP
n
to Q
n
or Q
n
1.5 7.0 1.5 8.0 1.5 8.4 ns
t
PHL
, t
PLH
Propagation Delay,
C
Dn
or S
Dn
to Q
n
or Q
n
1.5 7.0 1.5 8.0 1.5 8.4 ns
t
S
Setup Time 2.5 2.5 4.0 ns
t
H
Hold Time 1.5 1.5 2.0 ns
t
W
Pulse Width CP 3.3 3.3 4.0 ns
t
W
Pulse Width and C
D
, S
D
3.3 3.6 4.0 ns
t
REC
Recovery Time 2.5 3.0 4.5 ns
t
OSHL
, t
OSLH
Output to Output Skew
(4)
1.0 ns
74LCX74 Rev. 1.7.1 4