Datasheet

©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX573 Rev. 1.6.1 2
74LCX573 — Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs
Connection Diagrams
Pin Assignments for
SOIC, SOP, SSOP, TSSOP
Pad Assignments for DQFN
(Top View)
Pin Descriptions
Logic Symbol
Truth Table
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O
0
= Previous O
0
before HIGH-to-LOW transition of
Latch Enable
Functional Description
The LCX573 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is
HIGH, data on the D
n
inputs enters the latches. In this
condition the latches are transparent, i.e., a latch output
will change state each time its D input changes. When
LE is LOW the latches store the information that was
present on the D inputs a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE buffers are
controlled by the Output Enable (OE
) input. When OE is
LOW, the buffers are enabled. When OE is HIGH the
buffers are in the high impedance mode but this does not
interfere with entering new data into the latches.
Pin Names Description
D
0
–D
7
Data Inputs
LE Latch Enable Input
OE
3-STATE Output Enable Input
O
0
–O
7
3-STATE Latch Outputs
D
1
D
2
D
3
D
4
D
5
D
6
D
7
GND
D
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
O
0
LE
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
D
1
D
2
D
3
D
4
D
5
D
6
D
7
GND
D
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
LE
O
0
V
CC
120
2
3
4
5
6
7
8
9
10 11
19
18
17
16
15
14
13
12
OE
Inputs Outputs
OE LE D O
n
LHH H
LHL L
LLX O
0
HXX Z
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
O
0
OE
LE
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.
D
0
O
0
D
Q
LE
LE
OE
D
1
O
1
D
Q
LE
D
2
O
2
D
Q
LE
D
3
O
3
D
Q
LE
D
4
O
4
D
Q
LE
D
5
O
5
D
Q
LE
D
6
O
6
D
Q
LE
D
7
O
7
D
Q
LE
(Bottom View)
DAP
No Connect
Note: DAP (Die Attach Pad)