Datasheet

©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX374 Rev. 1.6.1 2
74LCX374 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs
Connection Diagrams
Pin Assignments for
SOIC, SOP, SSOP, TSSOP
Pad Assignments for DQFN
(Top View)
Pin Description
Logic Symbol
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
O
0
= Previous O
0
before HIGH-to-LOW of CP
Functional Description
The LCX374 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are com-
mon to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE
) LOW, the con-
tents of the eight flip-flops are available at the outputs.
When the OE is HIGH, the outputs go to the high imped-
ance state. Operation of the OE input does not affect the
state of the flip-flops.
Please note that this diagram is provided only for the
understanding of logic operations and should not be
used to estimate propagation delays.
Pin Names Description
D
0
–D
7
Data Inputs
CP Clock Pulse Input
OE
Output Enable Input
O
0
–O
7
3-STATE Outputs
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
O
0
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
O
7
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
O
0
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
O
7
V
CC
120
2
3
4
5
6
7
8
9
10 11
19
18
17
16
15
14
13
12
OE
Inputs Outputs
D
n
CP OE O
n
HLH
LLL
XLLO
0
XXHZ
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
O
0
OE
CP
O
1
O
2
O
3
O
4
O
5
O
6
O
7
(Bottom View)
DAP
No Connect
Note: DAP (Die Attach Pad)