Datasheet

©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX373 Rev. 1.8.1 2
74LCX373 — Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
Connection Diagrams
Pin Assignments for
SOIC, SOP, SSOP, TSSOP
Pad Assignments for DQFN
(Top View)
Pin Descriptions
Logic Symbols
Truth Table
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O
0
= Previous O
0
before HIGH-to-LOW transition
of Latch Enable
Functional Description
The LCX373 contains eight D-type latches with 3-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the D
n
inputs enters the latches. In this
condition the latches are transparent, i.e. a latch output
will change state each time its D input changes. When
LE is LOW, the latches store the information that was
present on the D inputs a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE standard
outputs are controlled by the Output Enable (OE
) input.
When OE is LOW, the standard outputs are in the
2-state mode. When OE is HIGH, the standard outputs
are in the high impedance mode but this does not inter-
fere with entering new data into the latches.
Pin Names Description
D
0
–D
7
Data Inputs
LE Latch Enable Input
OE 3-STATE Output Enable Input
O
0
–O
7
3-STATE Latch Outputs
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
O
0
D
7
D
6
O
6
O
5
D
5
D
4
O
4
O
7
LE
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
O
0
D
7
D
6
O
6
O
5
D
5
D
4
O
4
LE
O
7
V
CC
120
2
3
4
5
6
7
8
9
10 11
19
18
17
16
15
14
13
12
OE
Inputs Outputs
LE OE D
n
O
n
XHX Z
HLL L
HLH H
LLX O
0
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
O
0
OE
LE
O
1
O
2
O
3
O
4
O
5
O
6
O
7
IEEE/IEC
O
0
OE
LE
EN
C1
1DD
0
O
1
D
1
O
2
D
2
O
3
D
3
O
4
D
4
O
5
D
5
O
6
D
6
O
7
D
7
(Bottom View)
DAP
No Connect
Note: DAP (Die Attach Pad)