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74LCX32 — Low Voltage Quad 2-Input OR Gate with 5V Tolerant Inputs

74LCX32 Rev. 1.6.1

74LCX32

Features

■

5V tolerant inputs

■

2.3V–3.6V V

specifications provided

■

5.5ns t

max. (V

3.3V), 10

A I

max.

■

Power down high impedance inputs and outputs

■

±24mA output drive (V

3.0V)

■

Latch-up performance exceeds JEDEC 78 conditions

■

ESD performance:

– Human body model

2000V

– Machine model

150V

■

Leadless DQFN package

General Description

The LCX32 contains four 2-input OR gates. The inputs

tolerate voltages up to 7V allowing the interface of 5V

systems to 3V systems.

The 74LCX32 is fabricated with advanced CMOS tech-

nology to achieve high speed operation while maintain-

ing CMOS low power dissipation.

Ordering Information

Note:

1. DQFN package available in Tape and Reel only.

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order Number

Package

Number Package Description

74LCX32M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74LCX32SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LC32BQX

(1)

MLP14A 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC

MO-241, 2.5 x 3.0mm

74LCX32MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Implements

proprietary

noise/EMI reduction circuitry

Low Voltage Quad 2-Input OR Gate with 5V Tolerant Inputs

December 2013

Summary of content (13 pages)

PAGE 1
74LCX32 Low Voltage Quad 2-Input OR Gate with 5V Tolerant Inputs Features General Description ■ 5V tolerant inputs The LCX32 contains four 2-input OR gates. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. ■ 2.3V–3.6V VCC specifications provided ■ 5.5ns tPD max. (VCC = 3.3V), 10µA ICC max. ■ Power down high impedance inputs and outputs ■ ±24mA output drive (VCC = 3.
PAGE 2
74LCX32 — Low Voltage Quad 2-Input OR Gate with 5V Tolerant Inputs Connection Diagrams Logic Symbol Pin Assignments for SOIC, SOP, and TSSOP IEEE/IEC Pad Assignments for DQFN (Bottom View) (Top View) Pin Description Pin Names Description An, Bn Inputs On Outputs DAP No Connect Note: DAP (Die Attach Pad) ©1995 Fairchild Semiconductor Corporation 74LCX32 Rev. 1.6.1 www.fairchildsemi.
PAGE 3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VI Parameter Rating Supply Voltage –0.5V to +7.0V DC Input Voltage –0.5V to +7.
PAGE 4
TA = –40°C to +85°C Symbol VIH VIL VOH VOL II Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Leakage Current VCC (V) Min. 2.3–2.7 1.7 2.7–3.6 2.0 Max. 2.3–2.7 0.7 0.8 IOH = –100µA 2.3–3.6 V VCC – 0.2 2.3 IOH = –8mA 1.8 2.7 IOH = –12mA 2.2 3.0 IOH = –18mA 2.4 IOH = –24mA 2.2 V IOL = 100µA 0.2 2.3 IOL = 8mA 0.6 2.7 IOL = 12mA 0.4 3.0 IOL = 16mA 0.4 IOL = 24mA 0.55 0 ≤ VI ≤ 5.5V 2.3–3.6 2.3–3.
PAGE 5
TA = 25°C Symbol Parameter VCC (V) VOLP Quiet Output Dynamic Peak VOL 3.3 VOLV Quiet Output Dynamic Valley VOL Conditions Typical Unit CL = 50pF, VIH = 3.3V, VIL = 0V 0.8 V 2.5 CL = 30pF, VIH = 2.5V, VIL = 0V 0.6 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V –0.8 2.5 CL = 30pF, VIH = 2.5V, VIL = 0V –0.6 V Capacitance Symbol Typical Units Input Capacitance VCC = Open, VI = 0V or VCC 7 pF COUT Output Capacitance VCC = 3.
PAGE 6
Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V VCC x 2 at VCC = 2.5 ± 0.2V tPZH, tPHZ GND Figure 1. AC Test Circuit (CL includes probe and jig capacitance) Waveform for Inverting and Non-Inverting Functions 3-STATE Output Low Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic 3-STATE Output High Enable and Disable Times for Logic trise and tfall VCC Symbol 3.3V ± 0.3V 2.7V 2.5V ± 0.
PAGE 7
4LCX32 — Low Voltage Quad 2-Input OR Gate with 5V Tolerant Inputs Schematic Diagram (Generic for LCX Family) ©1995 Fairchild Semiconductor Corporation 74LCX32 Rev. 1.6.1 www.fairchildsemi.
PAGE 8
Tape Format for DQFN Package Designator Tape Section Number of Cavities Cavity Status Cover Tape Status BQX Leader (Start End) 125 (Typ.) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (Typ.) Empty Sealed Tape Dimensions inches (millimeters) Reel Dimensions inches (millimeters) Tape Size A B C D N W1 W2 12mm 13.0 (330.0) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4) 0.724 (18.4) ©1995 Fairchild Semiconductor Corporation 74LCX32 Rev. 1.
PAGE 9
74LCX32 — Low Voltage Quad 2-Input OR Gate with 5V Tolerant Inputs Physical Dimensions 8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 (0.33) 1.75 MAX 1.50 1.25 1.27 LAND PATTERN RECOMMENDATION M C B A SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS.
PAGE 10
74LCX32 — Low Voltage Quad 2-Input OR Gate with 5V Tolerant Inputs Physical Dimensions (Continued) Figure 4. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 11
74LCX32 — Low Voltage Quad 2-Input OR Gate with 5V Tolerant Inputs Physical Dimensions (Continued) Figure 5. 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 12
0.65 0.43 TYP 1.65 6.10 0.45 12.00° TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 6. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.
PAGE 13
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