Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsLogic ICsLogic IC - Demultiplexer, decoder Decoder/demultiplexer Single supply TSSOP 16

March 1995

Revised December 2013

74LCX138 Low Voltage 1-of-8 Decoder/Demultiplexer with 5V Tolerant Inputs

74LCX138

Low Voltage 1-of-8 Decoder/Demultiplexer

with 5V Tolerant Inputs

General Description

The LCX138 is a high-speed 1-of-8 decoder/demultiplexer.

This device is ideally suited for high-speed memory chip

select address decoding. The multiple input enables allow

parallel expansion to a 1-of-24 decoder using just three

LCX138 devices or a 1-of-32 decoder using four LCX138

devices and one inverter.

The 74LCX138 is fabricated with advanced CMOS technol-

ogy to achieve high speed operation while maintaining

CMOS low power dissipation.

Features

■ 5V tolerant inputs

■ 2.3V to 3.6V V

specifications provided

■ 6.0 ns t

max (V

3.3V), 10

A I

max

■ Power down high impedance inputs and outputs

■

24 mA output drive (V

3.0V)

■ Implements patented noise/EMI reduction circuitry

■ Latch-up performance exceeds 500 mA

■ ESD performance:

Human body model

2000V

Machine model

200V

■ Leadless DQFN package

Ordering Code:

Note 1: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Note 2: DQFN package available in Tape and Reel only.

Order Number

Package

Number

Package Description

74LCX138M

(Note 1)

M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74LCX138SJ

(Note 1)

M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LCX138BQX

(Note 2)

MLP016E 16-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241,

2.5 x 3.5mm

74LCX138MTC

(Note 1)

MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

2013

Summary of content (12 pages)

PAGE 1
Revised December 2013 74LCX138 Low Voltage 1-of-8 Decoder/Demultiplexer with 5V Tolerant Inputs General Description Features The LCX138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LCX138 devices or a 1-of-32 decoder using four LCX138 devices and one inverter.
PAGE 2
74LCX138 Connection Diagrams Pin Descriptions Pin Assignments for SOIC, SOP, and TSSOP Pin Names Description A0–A2 Address Inputs E1–E2 Enable Inputs E3 Enable Input O0–O7 Outputs DAP No Connect Note: DAP (Die Attach Pad) Pad Assignments for DQFN Functional Description The LCX138 high-speed 1-of-8 decoder/demultiplexer accepts three binary weighted inputs (A0, A1, A2) and, when enabled, provides eight mutually exclusive activeLOW outputs (O0–O7).
PAGE 3
74LCX138 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.
PAGE 4
74LCX138 Absolute Maximum Ratings(Note 3) Symbol Parameter Value Conditions VCC Supply Voltage −0.5 to +7.0 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage IIK DC Input Diode Current −50 VI < GND IOK DC Output Diode Current −50 VO < GND +50 VO > VCC Units V V −0.5 to VCC + 0.
PAGE 5
TA = −40°C to +85°C, RL = 500Ω Symbol Parameter VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5V ± 0.2V CL = 50pF CL = 50pF CL = 30pF Min Max Min Max Min Max tPHL Propagation Delay 1.5 6.0 1.5 7.0 1.5 7.2 tPLH An to Qn 1.5 6.0 1.5 7.0 1.5 7.2 tPHL Propagation Delay 1.5 6.5 1.5 7.5 1.5 8.4 tPLH E3 to Qn 1.5 6.5 1.5 7.5 1.5 8.4 tPHL Propagation Delay 1.5 6.0 1.5 7.0 1.5 7.2 tPLH E1 or E2 to Qn 1.5 6.0 1.5 7.0 1.5 7.
PAGE 6
74LCX138 AC Loading and Waveforms Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3V ± 0.3V VCC x 2 at VCC = 2.5V ± 0.
PAGE 7
4LCX138 Schematic Diagram Generic for LCX Family 7 www.fairchildsemi.
PAGE 8
74LCX138 Tape and Reel Specification Tape Format for DQFN Package Designator BQX Tape Number Cavity Section Cavities Status Cover Tape Status Leader (Start End) 125 (typ) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (typ) Empty Sealed TAPE DIMENSIONS inches (millimeters) REEL DIMENSIONS inches (millimeters) Tape Size 12 mm A B C D N W1 W2 13.0 0.059 0.512 0.795 2.165 0.488 0.724 (330.0) (1.50) (13.00) (20.20) (55.00) (12.4) (18.4) www.
PAGE 9
74LCX138 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 9 www.fairchildsemi.
PAGE 10
74LCX138 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.
PAGE 11
74LCX138 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.5mm Package Number MLP016E 11 www.fairchildsemi.
PAGE 12
74LCX138 Low Voltage 1-of-8 Decoder/Demultiplexer with 5V Tolerant Inputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.