Datasheet

©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX00 Rev. 1.7.1 2
74LCX00 — Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
Connection Diagrams
Pin Assignments for SOIC, SOP, and TSSOP
Pad Assignments for DQFN
(Top View)
Pin Description
Logic Symbol
IEEE/IEC
Pin Names Description
A
n
, B
n
Inputs
O
n
Outputs
(Bottom View)
DAP
No Connect
Note: DAP (Die Attach Pad)