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74AC245, 74ACT245 — Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs

74AC245, 74ACT245 Rev. 1.5.0

January 2008

74AC245, 74ACT245

Octal Bidirectional Transceiver with 3-STATE

Inputs/Outputs

Features

■

and I

reduced by 50%

■

Non-inverting buffers

■

Bidirectional data path

■

A and B outputs source/sink 24mA

■

ACT245 has TTL-compatible inputs

General Description

The AC/ACT245 contains eight non-inverting bidirec-

tional buffers with 3-STATE outputs and is intended for

bus-oriented applications. Current sinking capability is

24mA at both the A and B ports. The Transmit/Receive

(T/R

) input determines the direction of data flow through

the bidirectional transceiver. Transmit (active-HIGH)

enables data from A ports to B ports; Receive (active-

LOW) enables data from B ports to A ports. The Output

Enable input, when HIGH, disables both A and B ports

by placing them in a HIGH Z condition.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order Number

Package

Number Package Description

74AC245SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74AC245SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74AC245MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

74AC245PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

74ACT245SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74ACT245SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74ACT245MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

74ACT245MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

74ACT245PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Summary of content (12 pages)

PAGE 1
74AC245, 74ACT245 Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs Features General Description ■ ICC and IOZ reduced by 50% ■ Non-inverting buffers The AC/ACT245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus-oriented applications. Current sinking capability is 24mA at both the A and B ports. The Transmit/Receive (T/R) input determines the direction of data flow through the bidirectional transceiver.
PAGE 2
Logic Symbol IEEE/IEC Pin Description Pin Names Description OE Output Enable Input T/R Transmit/Receive Input A0–A7 Side A 3-STATE Inputs or 3-STATE Outputs B0–B7 Side B 3-STATE Inputs or 3-STATE Outputs Truth Table Inputs OE T/R Outputs L L Bus B Data to Bus A L H Bus A Data to Bus B H X HIGH-Z State H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial ©1988 Fairchild Semiconductor Corporation 74AC245, 74ACT245 Rev. 1.5.0 www.fairchildsemi.
PAGE 3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC IIK Parameter Rating −0.5V to +7.0V Supply Voltage DC Input Diode Current VI = −0.5V −20mA VI = VCC + 0.
PAGE 4
TA = +25°C Symbol Parameter VCC (V) VIH Minimum HIGH Level Input Voltage 3.0 Conditions VOUT = 0.1V or VCC – 0.1V Maximum LOW Level Input Voltage 2.1 2.1 2.25 3.15 3.15 2.75 3.85 3.85 1.5 0.9 0.9 2.25 1.35 1.35 2.75 1.65 1.65 2.99 2.9 2.9 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 2.56 2.46 3.86 3.76 4.86 4.76 4.5 3.0 4.5 VOUT = 0.1V or VCC – 0.1V 5.5 VOH Minimum HIGH Level Output Voltage Guaranteed Limits 1.5 5.5 VIL Typ. TA = −40°C to +85°C 3.0 3.
PAGE 5
TA = +25°C Symbol Parameter VCC (V) VIH Minimum HIGH Level Input Voltage 4.5 5.5 Maximum LOW Level Input Voltage VIL VOH Minimum HIGH Level Output Voltage Conditions Typ. TA = −40°C to +85°C Guaranteed Limits VOUT = 0.1V or VCC − 0.1V 1.5 2.0 2.0 1.5 2.0 2.0 VOUT = 0.1V or VCC − 0.1V 1.5 0.8 0.8 5.5 1.5 0.8 0.8 4.5 IOUT = −50µA 4.49 4.4 4.4 4.5 5.5 4.5 5.49 VIN = VIL or VIH, 5.4 5.4 3.86 3.76 4.86 4.76 0.1 0.1 Units V V V IOH = −24mA 5.
PAGE 6
TA = +25°C, CL = 50pF VCC (V)(6) Min. Propagation Delay, An to Bn or Bn to An 3.3 1.5 5.0 5.0 1.5 Propagation Delay, An to Bn or Bn to An 3.3 5.0 Output Enable Time Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Output Enable Time Output Disable Time Output Disable Time TA = −40°C to +85°C, CL = 50pF Typ. Max. Min. Max. Units 8.5 1.0 9.0 ns 3.5 6.5 1.0 7.0 1.5 5.0 8.5 1.0 9.0 1.5 3.5 6.0 1.0 7.0 3.3 2.5 7.0 11.5 2.0 12.5 5.0 1.5 5.0 8.5 1.0 9.0 3.3 2.5 7.
PAGE 7
13.00 12.60 A 11.43 20 11 B 9.50 10.65 7.60 10.00 7.40 2.25 1 PIN ONE INDICATOR 10 0.51 0.35 0.25 M 0.65 1.27 1.27 C B A LAND PATTERN RECOMMENDATION 2.65 MAX SEE DETAIL A 0.33 0.20 C 0.75 0.25 X 45° SEATING PLANE NOTES: UNLESS OTHERWISE SPECIFIED (R0.10) GAGE PLANE (R0.10) 0.10 C 0.30 0.10 0.25 8° 0° A) THIS PACKAGE CONFORMS TO JEDEC MS-013, VARIATION AC, ISSUE E B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) CONFORMS TO ASME Y14.
PAGE 8
74AC245, 74ACT245 — Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs Physical Dimensions (Continued) Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 9
74AC245, 74ACT245 — Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs Physical Dimensions (Continued) Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 10
26.92 24.89 7.11 6.09 PIN #1 (0.97) 1.78 1.14 2.54 0.36 0.56 .001[.025] 3.43 3.17 5.33 MAX 7° TYP 7.87 7° TYP 3.55 3.17 0.38 MIN 7.62 10.92 MAX 0.20 0.35 C NOTES: Figure 4. 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice.
PAGE 11
74AC245, 74ACT245 — Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs Physical Dimensions (Continued) Figure 5. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 12
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