User guide

Edge, level, and shape variations impact width, height, and symmetry of the eye
opening. An example is shown below:
How the N4903 Generates Jitter
An Serial BERT on which the calibrated and integrated jitter injection option J10
and the interference channel option J20 are installed, combines all the necessary
jitter sources in one instrument.
Jitter Generation Block Diagram
To support all present test standards, the pattern generator of the Serial BERT has
the following hardware architecture:
sRJ
PJ1
Clock
Modulator
Delay Modulation
(220ps)
Delay Modulation
(220ps)
RJ
BUJ
ExternalExternal Delay
+
+
+
220ps Data & Aux Data on
220ps Forwarded Clock on
Clock
Trigger / Ref Clock
Data
Aux Data
Delay Modulation
(610ps)
Clock & Data
Modulation Signal
Functional Coupling
Jitter Delay
SSC
rSSC
SJ
PJ2
Internal Clock
Oscillator
PLL
6.75Gb/ … 12.5Gb/s
External Clock
150Mb/s … 12.5Gb/s
620Mb/s … 12.5Gb/s
Clock source selection
x÷y
1÷z
Aux Clock
÷1 or ÷2
÷n
+
The clock can be generated from the internal oscillator or an external source.
The instrument has internal sources for spread spectrum clocking (SSC), residual
Spread Spectrum Clock (rSSC), sinusoidal jitter (SJ), two periodic jitter sources
(PJ-1 and PJ-2), bounded uncorrelated jitter (BUJ), Random Jitter (RJ) and
spectrally distributed Random Jitter (sRJ), which is composed by using the BUJ
Jitter Tolerance Tests 8
Agilent J-BERT N4903B High-Performance Serial BERT 401
Clock generator
Jitter sources